Modeling and Simulation ITWG
1 / 19

Modeling and Simulation ITWG Jürgen Lorenz - FhG-IISB - PowerPoint PPT Presentation

  • Uploaded on

Modeling and Simulation ITWG Jürgen Lorenz - FhG-IISB. ITWG/ TWG Members. H. Jaouen, STM * W. Molzer, Infineon * R. Woltjer, Philips * G. Le Carval, LETI J. Lorenz, Fraunhofer IIS-B * W. Schoenmaker, IMEC * supported by EC User Group UPPER+ T. Wada, SELETE S. Sato, Fujitsu

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
Download Presentation

PowerPoint Slideshow about ' Modeling and Simulation ITWG Jürgen Lorenz - FhG-IISB' - pello

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

Modeling and Simulation ITWG

Jürgen Lorenz - FhG-IISB

ITWG/TWG Members

H. Jaouen, STM*

W. Molzer, Infineon*

R. Woltjer, Philips*

G. Le Carval, LETI

J. Lorenz, Fraunhofer IIS-B*

W. Schoenmaker, IMEC

* supported by EC User Group UPPER+


S. Sato, Fujitsu

Japanese TWG 16 industrial members

C. Riccobene, AMD

M. Giles, INTEL

M. Orlowski, Motorola

M. Meyyappan, NASA


J. Wu, TI

E. Hall, Arizona State Univ.

J.-H. Choi, Hynix

K.H. Lee, Samsung

Key Messages (I)

  • Update of key messages from 2001/2002 ITRS:

  • Technology modeling and simulation is one of a few enabling methodologies that can accelerate development times and reduce development costs: Assessment up to 35% in 2003

  •  important not only in years of difficult economic conditions

  • Modeling and simulation provides an ‘embodiment of knowledge and understanding’. It is a tool for technology/device optimization and also for training/education

  • Accurate experimental characterization is essential

  • Art of modeling:

  • - Combine different experiments & theory to extract physical mechanisms

  • & parameters

  • - Find appropriate trade-off between detailed physical simulation (CPU and

  • memory costly) and simplified but physically appropriate approaches

Key Messages (II)

  • Further growing importance of atomistic/hierarchical/multilevel simulation, materials - appropriate treatment of nanostructures

  • Extension of cross-cut links to the other ITRS sections ongoing process

  • Specific problem for 2003

  • - Delays in guidelines, + travel restrictions at companies

  • - Need for additional participation esp. from Korea, Taiwan, and partly

  • also USA

M& S 2003 Sequence of Actions

  • Requirements: Update 2003 & critically review & simplify 2003 tables

  • (still valid details into text) - also for readability and preparation for 2004

  • • Critically update challenges (timing and content)

  • Consider transition into Nano Era

  • Further strengthen interactions with other ITWGs

  • (esp. around San Francisco meeting)

  • ITWG composition: Updates in US and Japan on the way/done,

  • more contributions from Korea and Taiwan needed

Technology Modeling SCOPE & SCALES

  • Equipment related

    • Equipment/feature scale

    • Lithography

  • Feature scale

    • Front End, Back End

    • Device

2001/2 Chapter sub-sections in blue - (slight changes in 2003 in progress)

  • IC-scale

  • Circuit elements

  • Package modeling

  • Interconnect performance modeling

•Materials Modeling

•Numerical Methods

Short-Term Challenges: Major Changes

  • Modeling hierarchy included  “Modeling of shallow junctions” extended

  • to “Front-End Process Modeling for Nanometer Structures”

  • • “Ultimate nano-scale CMOS simulation capability” pulled in from long-term, replacing & partly incorporating “Gate-stack models for ultra-thin dielectrics” (phenomenological models)

  • • Rest of “Gate-stack models for ultra-thin dielectrics”incorporated into new long-term challenge on predictive “Modeling of processing and electrical properties of new materials“

  • • 2002 long-term challenge “Thermal-Mechanical-Electrical Modeling for interconnections and packaging“ pulled in to short-term (6th short-term challenge)

  • More precise phrasing & shift of emphasis / new aspects in other

  • challenges

Short-term Difficult Challenges

High-Frequency Circuit Modelingfor 5-40 Ghz applications

  • Needs

  • Efficient extraction and simulation of full-chip interconnect delay

  • Accurate and yet efficient 3D interconnect models, esp. for transmission lines and S-parameters

  • High-frequency circuit models including

    • non-quasi-static effects

    • substrate noise

    • parasitic coupling

  • Parameter extraction assisted by numerical electrical simulation instead of RF measurement

(From Philips)

Short-Term Difficult Challenges

Front-End Process Modeling for Nanometer Structures


  • Diffusion/activation/damage models and parameters incl. low thermal budget processes in Si-based substrate, e.g. Si, SiGe:C, (incl. strain), SOI and ultra-thin body devices

  • Characterization tools for ultra-shallow geometries and dopant levels

  • Modeling hierarchy from atomistic to continuum for dopants and defects in bulk and at interfaces

Source: A. Claverie, CEMES/CNRS, Toulouse, France

Short-Term Difficult Challenges

Modeling of Equipment Influences on Features Generated in Deposition and Etching Processes


  • Fundamental physical data ( e.g. rate constants, cross sections, surface chemistry); reaction mechanisms and reduced models for complex chemistries

  • Linked equipment/feature scale models

  • CMP (full wafer and chip level, pattern dependent effects)

  • •MOCVD, PECVD and ALD modeling

  • • Multi-generation equipment/wafer models

Simulated across-wafer variation of feature profile for a sputter-deposited barrier.

Short-Term Difficult Challenges

Lithography Simulation including NGL


  • Optical simulation of resolution enhancement techniques including mask optimization (OPC, PSM)

  • Predictive resist models incl. line-edge roughness, etch resistance and mechanical stability

  • Multi-generation lithography system models

Printing of defect on phase-shift mask: bump defect (top) vs. etch defect (lower)

Short-Term Difficult Challenges

Ultimate nanoscale CMOS simulation capability

Pulled in from long-term!


• Methods and algorithms which contribute to prediction of CMOS limits

• Quantum based simulators

• Models and analysis to enable design and evaluation of devices and

architectures beyond traditional planar CMOS

• Phenomenological gate stack models for ultra-thin dielectrics

• Models for device impact of statistical fluctuations in structures and dopant


Short-Term Difficult Challenges

Thermal-Mechanical-Electrical Modeling for interconnections and packaging

Pulled in from long-term!


• Model thermal-mechanical and electronic properties of Low-k, High-k

and conductors and the impact of processing on these properties

• Model reliability of packages and interconnects, e.g. Stress voiding,

electromigration, piezoelectric effects; textures, fracture, adhesion

Long-Term Challenges: Major Changes

  • “Extend beyond continuum tools” shifted to short-term & integrated there

  • into various challenges, esp. “Front-End Process Simulation”

  • Instead: “Modeling of processing and electrical properties of new materials”

  • “Ultimate nanoscale CMOS simulation capability“ shifted to short-term, including parts of old „gate stack modeling“ challenge

  • “Thermo-Mechanical-Electrical Modeling for Interconnections and Packaging” shifted to short-term

  • “Software Module Integration” skipped: Rather a requirement than a

  • challenge

  • Instead: “Nano-Scale Modeling” (e.g. nanotubes ...)

  • New challenge “Optoelectronics modeling”

Short-Term Requirement: Major Changes


- Some items now in “zebra” colour - according to ITRS guidelines:

“Limitations of available solutions will not delay the start of production. In some cases, work-arounds will be initially employed. Subsequent improvement is expected to close any gaps for production performance in areas such as process control, yield, and productivity.“

- This means for simulation: It can be used, but with more calibration, larger CPU time/memory, less generality then in the end required ...

Short-Term Requirement: Major Changes


- In exposure simulation no more emphasis on evaluation of wavelengths, but on capabilities of simulation incl. mask features and CPU efficiency

Gate stack:

- Short-term focus on high-k

- “Alternative” dielectrics / gates tbd with PIDS

Back-End Process/Equipment/Topography Modeling

- More clear structure, according to kinds of processes to be simulated

Short-Term Requirement: Major Changes

Numerical device modeling:

- Instead of “bulk CMOS” and “non-bulk” CMOS now “Classical CMOS” and “Non-classical CMOS devices”

“Circuit element modeling/ECAD” replaced by

“circuit component modeling”& now structured into

- Active devices

- Interconnects and integrated passives

Package modeling now structuring into

- Electrical modeling

- Thermo-mechanical modeling

instead of an item “thermo-mechanical-electrical integrated models”