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Ultra-Low Voltage Circuits andProcessor in 180nm to 90nmTechnologies with aSwapped-Body Biasing TechniqueS. Narendra, J. Tschanz, J. Hofsheier, B. Bloechel,S. Vangal, Y. Hoskote, S. Tang, D. Somasekhar,Microprocessor Research, Intel LabsInstructor : Dr.fakhraeiPresented by : Elaheh RahmaniDate : 83.10.10

outline
Outline
  • Motivation
  • Forward body bias overview
  • Low-voltage swapped-body concept
  • Measurement results

-180nm and 130nm test circuits

-90nm TCP offload processor

  • Summary
motivation
Motivation:
  • For ultra-low-energy processors, Vcc is

reduced to improve energy efficiency while

meeting relaxed frequency targets.

  • However Vcc reduction by conventional

schemes are limited by:

(1) Leakage power becoming a larger fraction of total power at low Vcc

(2) Severe delay degradation below a certain Vcc

(3) Circuit failure at very low Vcc

forward body bias fbb
Forward Body Bias (FBB):
  • VB = VS :

No Body Bias (NBB)

  • VB < VS :

Forward Body Bias (FBB)

impact of fbb
Impact of FBB:

VB = VS : VBS = 0 : NBB

VB < VS : VBS < 0 : FBB 􀃎 VTP↓

lvsb characteristics
LVSB characteristics:
  • LVSB provides FBB value of Vcc
  • In the LVSB mode, changing Vcc produces

different VT values automatically without

needing process change

  • But, LVSB is more sensitive to supply and

ground noise

  • Unlike conventional FBB, LVSB circuits do

not need body bias generators

  • LVSB circuits has lower VT and better short

channel effect than NBB

tcp processor core
TCP processor core:

TCP=Transmission control protocol

TCB=Transmission control block

CLB= connection look up block

ROB= Reorder block

measurement summary
Measurement summary:
  • LVSB provides FBB value of Vcc without

body bias generators

  • Compared to NBB, LVSB enables

– Over 60% frequency improvement at 500mV

– Over 70mV Vcc reduction for iso-frequency

– Vccmin reduction of more than 10%

– Dynamic LVSB reduces standby power to

NBB while providing active operation benefits

references
References:
  • [1] S.Narendra, J.Tschanz, “Ultra-Low Voltage Circuits and Processor in 180nm to 90nm Technologies with a Swapped-Body Biasing Technique,”2004 IEEE ISSCC.0-7803-8267-6/04
  • [2] Y. Hoskote et al., “A 10GHz TCP Offload Accelerator for 10Gb/s Ethernet in 90nm Dual-Vt CMOS,” ISSCC Dig. Tech. Papers., pp. 258-259, Feb. 2003.
  • [3] S. Narendra et al., “1.1V 1GHz Communications Router with On-Chip Body Bias in 150nm CMOS,” ISSCC Dig. Tech. Papers., pp. 270-271, Feb. 2002.
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