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Scalable Packet Classification Using Interpreting -- Cross-platform Multi-core Solution. Haipeng Cheng & Bei Hua Univ. of Science & Technology of China (USTC). Xinan Tang Intel Compiler Lab. Outline. Background Packet Classification Problem Review RFC Algorithm TIC Algorithm

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Xinan tang intel compiler lab

Scalable Packet Classification Using Interpreting

-- Cross-platform Multi-core Solution

Haipeng Cheng & Bei Hua

Univ. of Science & Technology of China (USTC)

Xinan Tang

Intel Compiler Lab.

Intel Compiler Lab and USTC, PPoPP’08


Outline

  • Background

  • Packet Classification Problem

  • Review RFC Algorithm

  • TIC Algorithm

  • Experimental Results and Analysis

  • Future Work

Intel Compiler Lab and USTC, PPoPP’08


10gbe smaller chapter and denser
10GbE Smaller, Chapter, and Denser

Intel Compiler Lab and USTC, PPoPP’08


Background networking
Background (Networking)

  • 10Gbps offers too much bandwidth for the multi-core computers to handle

  • Traffic complexity: triple-play (voice, video, and data) support is essential

  • Traffic types: P2P packets occupy 70% of the total network traffic

  • Packet classification becomes increasingly important to identify and control the traffic

Intel Compiler Lab and USTC, PPoPP’08


Background multi core
Background (Multi-core)

  • Multi-core becomes prevalent

    • Networking (Intel IXP, Cavium Octeon, RMI XLR)

    • Multi-media (IBM Cell, Intel Larabee)

    • General-purpose

      • Intel Core 2 Duo

      • AMD Barcelona

      • IBM Power5

      • Sun Niagara

Comment: find an efficient solution for one multi-core architecture is hard; find a cross-platform solution even harder

Intel Compiler Lab and USTC, PPoPP’08


Classification problem
Classification Problem

  • The process of partitioning packets into “groups” is called packet classification.

    • Packet classification typically uses 5-tuples

    • Enable value-added services:

      • Security: classify packets based on security policies

      • QoS: sort packets and ensure the packets receiving an appropriate bandwidth share

      • P2P management: tame the P2P traffic

Intel Compiler Lab and USTC, PPoPP’08


Packet Classification Example

Which package does it match to ?

How to match?

Packet (000, 010)

Intel Compiler Lab and USTC, PPoPP’08


Why is packet classification hard
Why Is Packet Classification Hard?

  • Packet classification is NP-hard

  • Heuristic solutions seek O(1) solutions

  • At 10Gbps (OC-192) speed, a 64-byte packet needs to be classified within 40ns

    • one DARM access time

    • 100 cycles for a 2.5Ghz CPU

Intel Compiler Lab and USTC, PPoPP’08


Packet classification solutions
Packet Classification Solutions

  • At 10Gbps (OC-192) speed, it is done by

    • Special ASIC

    • TCAM

    • Algorithms (?)

      • Hierarchical Tries

      • Recursive Flow Classification (RFC)

      • Two-stage Interpreter based Classification (TIC)

Intel Compiler Lab and USTC, PPoPP’08


Rfc example
RFC Example

  • Even though search space is huge (2^3)*(2^3)*(2^3), for a given packet, the actual matched rules per field is limited

  • Class bitmap can be used to describe the matched rules:

    • 0001 means R4 is the matched rule

    • 1101 means R1, R2, and R4 are the ones matched

Intel Compiler Lab and USTC, PPoPP’08


Rfc exam
RFC Exam.

Intel Compiler Lab and USTC, PPoPP’08


Map an S-bit string concatenated from the d fields of the packet header to a T-bit number through multiple phases (T << S )

Recursive Flow Classification

S-IP(32b)

D-IP(32b)

S-Port(16b)

D-Port(16b)

Proto(8b)

Intel Compiler Lab and USTC, PPoPP’08


What s wrong with rfc
What’s Wrong with RFC?

  • Memory exploded

  • Too slow to do update in practice

  • However, 13-memory-access is the fastest classification algorithm

Intel Compiler Lab and USTC, PPoPP’08


Two stage interpreting based classification
Two-stage Interpreting based Classification

  • Domain knowledge: divide the RFC into two stages:

    • Search source-destination prefix pair

      • 99.9% of the time the number of rules that match a pair of source-destination prefix is no more than 5

    • Search the list of port-range expressions

      • Range [2..14] in prefix: 001*, 01**, 10**, 110*, 1110

      • Range search is based on calculation (<,>,=)

      • Encoding the type of the range expressions intelligently

      • Evaluating them sequentially

Intel Compiler Lab and USTC, PPoPP’08


Tic main ideas
TIC Main Ideas

  • L2 cache size is in the range of mega-bytes

  • Network applications are memory intensive

  • Memory is best accessed sequentially

    • 64bytes cache line size for Core 2 Duo

    • 64bytes local-memory for IXP

  • Can compression be used to optimize performance?

    • CISC encoding for smaller memory footprint

Intel Compiler Lab and USTC, PPoPP’08


Putting everything together
Putting Everything Together

  • Domain knowledge: two-stage classification

  • Architecture features:

    • Plenty of CPU cycles

    • Large L2 cache

    • Block based sequential access

    • Branch prediction can eliminate infrequent executed paths

Intel Compiler Lab and USTC, PPoPP’08


Port range expressions
Port-Range Expressions

  • There are five type of range expressions

    • WC (wildcard)

    • HI ([1024, 65535])

    • LO ([0, 1023])

    • AR (arbitrary range)

    • EM (exact match)

  • For (s-port, d-port, proto), there are at least 5x5x2=50 operators

Intel Compiler Lab and USTC, PPoPP’08


Characteristics of range expressions for destination port
Characteristics of Range Expressions for Destination Port

Intel Compiler Lab and USTC, PPoPP’08


Encoding and interpreting
Encoding and Interpreting

  • Eliminate WC calculation

  • Introduce HI and LO operators without storing the constants

    • HI ([1024, 65535])

    • LO ([0, 1023])

  • Store AR and EM parameters in the operand fields

  • NOP for code block alignment

Intel Compiler Lab and USTC, PPoPP’08


Can we afford to increase operator
Can we afford to increase #operator?

  • Interpreter is a big switch-case statement.

  • Compiler stores the starting address of each case in a jump table.

  • Interpreter executes two instructions per iteration:

    • load an address into a register from the jump table

    • jump to the address in the indirect addressing mode

  • IXP –E compiler can optimize switch-case with

    • Default Case Removal

    • Switch Block Packing

Intel Compiler Lab and USTC, PPoPP’08


Experimental setup
Experimental Setup

  • Intel Xeon 5160 Core 2 Duo running at 3.00GHz with 4MB L2 cache and a 1333MHz system bus

  • Cycle-accurate IXP2800 simulator, and each ME runs at 1.2GHz with 8 threads

  • Generate packet traces from ClassBench, and use the low locality traces to cancel the locality

Intel Compiler Lab and USTC, PPoPP’08


Space reduction
Space Reduction

Intel Compiler Lab and USTC, PPoPP’08


Relative speedups on core 2 duo
Relative Speedups on Core 2 Duo

Intel Compiler Lab and USTC, PPoPP’08


Speedups on ixp rfc vs tic
Speedups on IXP (RFC vs. TIC)

Intel Compiler Lab and USTC, PPoPP’08


Why rfc is better than tic on ixp
Why RFC is better than TIC on IXP?

Block size plays an important role in the IXP architecture since SRAM is optimized for 32bit access

Intel Compiler Lab and USTC, PPoPP’08


Block size impacts on ixp
Block Size Impacts on IXP

Intel Compiler Lab and USTC, PPoPP’08


Future work
Future Work

  • Improve TIC performance on IXP

  • Improve TIC performance on firewall rules

  • Improve update speeds

Intel Compiler Lab and USTC, PPoPP’08


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