Predicting Performance Impact of DVFS
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Predicting Performance Impact of DVFS for Realistic Memory Systems. Rustam Miftakhutdinov Eiman Ebrahimi Yale N. Patt. Dynamic Voltage/Frequency Scaling. V. f. Image source: intel.com. Impact of Frequency Scaling. time. energy. power. f opt. frequency. Impact of Frequency Scaling.

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Predicting Performance Impact of DVFS for Realistic Memory Systems

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Predicting performance impact of dvfs for realistic memory systems

Predicting Performance Impact of DVFSfor Realistic Memory Systems

Rustam Miftakhutdinov

EimanEbrahimi

Yale N. Patt


Dynamic voltage frequency scaling

Dynamic Voltage/Frequency Scaling

V

f

Image source: intel.com


Impact of frequency scaling

Impact of Frequency Scaling

time

energy

power

fopt

frequency


Impact of frequency scaling1

Impact of Frequency Scaling

time

power

fo

frequency


Prediction overview

Prediction Overview

our work

time

energy per

instruction

energy

fo

freq.

×

fopt

fo

fopt

freq.

power

frequency

fo

fo

freq.

0

100K

200K

300K

instructions


Outline

Outline

Intro to performance prediction

Why realistic memory systems?

Variable memory latency

Prefetching


Why realistic memory system

Why Realistic Memory System?

V

f


Prior work

Prior Work

  • Stall time

  • Leading loads (2010)

    S. Eyerman et al.

    G. Keramidas et al.

    B. Rountree

Evaluated withconstant access latency memory system


Energy savings

Energy Savings

*

Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006


Energy savings1

Energy Savings

*

Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006


Outline1

Outline

Intro to performance prediction

Why realistic memory systems?

Variable memory latency

Prefetching


Execution example

Execution Example

C

memory

requests

B

D

A

E

chip

activity

1

2

3

4

time


T t memory t compute

T = Tmemory + Tcompute

independent offrequency

proportional tocycle time


Linear model

Linear Model

execution time T

Tcompute

Tmemory

to

0

cycle time t


Measuring t memory

Measuring Tmemory

memory

requests

chip

activity

time


Measuring t memory1

Measuring Tmemory

memory

requests

chip

activity

time


Causes of request dependences

Causes of Request Dependences

Pointer Chasing

Finite Chip Resources

next

miss

miss

next

instruction window

next


Measuring t memory2

Measuring Tmemory

memory

requests

chip

activity

time


Critical path algorithm

Critical Path Algorithm

new Tmemory

at Tstart1. record Tstart and Tmemory

Tmemory

(length of critical path)

time

old critical path

request latency

at Tend2. compute path= Tmemory(Tstart) + (Tend - Tstart)

  • 3. set Tmemory= max(Tmemory, path)

Tend

Tstart


Linear model1

Linear Model

execution time T

Tcompute

Tmemory

to

0

cycle time t


Linear model2

Linear Model

time

execution time T

fo

freq.

energy

time

Tcompute

×

Tm

Tmemory

to

cycletime

fo

fopt

freq.

power

fo

freq.

to

0

cycle time t


Critical path variable access latency

Critical Path: Variable Access Latency

memory

requests

chip

activity

time

Leading Loads: Constant Access Latency

memory

requests

chip

activity

time


Leading loads

Leading Loads

execution time T

leading loads

Tcompute

Tmemory

to

0

cycle time t


Leading loads1

Leading Loads

time

execution time T

leading loads

fo

freq.

energy

time

Tcompute

×

Tm

Tmemory

to

cycletime

fo

fopt

freq.

power

fo

freq.

to

0

cycle time t


Energy savings2

Energy Savings

*

Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006


Outline2

Outline

Intro to performance prediction

Why realistic memory systems?

Variable memory latency

Prefetching


Streaming workload

Streaming Workload

Prefetcher ON Frequency +500 MHz

Prefetcher ON Frequency+200 MHz

Prefetcher OFF

Prefetcher ON

memory

requests

memory

requests

memory

requests

memory

requests

chip

activity

chip

activity

chip

activity

chip

activity

time

time

time

time


Limited bandwidth model

Limited Bandwidth Model

execution time T

Tcompute

Tmemory

min

Tdemand

tcrossover

0

cycle time t


Energy savings3

Energy Savings

*

Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks.Baseline: most energy-efficient static frequency for SPEC 2006


Recap

Recap

Intro to performance prediction

Why realistic memory systems?

Variable memory latency

Prefetching


Final thought

Final Thought

Performance predictors need realistic evaluation


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