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Upgrade Proposal for the ATF Damping Ring BPM Downconverter Front-end – Fermilab Activities –

Upgrade Proposal for the ATF Damping Ring BPM Downconverter Front-end – Fermilab Activities –. Manfred Wendt for the Fermilab ATF DR BPM collaboration efforts. Reminder: BPM Hardware Overview. 4 button BPM pickup. Upgrade Proposal. Down Mix. CAL. 4. LPF. BPF. PLL. 4. CTRL. LO (729).

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Upgrade Proposal for the ATF Damping Ring BPM Downconverter Front-end – Fermilab Activities –

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  1. Upgrade Proposal for the ATF Damping Ring BPM Downconverter Front-end– Fermilab Activities – Manfred Wendt for the Fermilab ATF DR BPM collaboration efforts

  2. Reminder: BPM Hardware Overview 4 button BPM pickup Upgrade Proposal Down Mix CAL 4 LPF BPF PLL 4 CTRL LO (729) IF (15) beam beam Position (EPICS) CLK (64.9) I VME µP Motorola 5500 Dig. Receiv. Echotek Timing Digital I/O VME TRG Q 714 INJ Cal (~ 714) 2.16 VME BUS Global Design Effort

  3. Motivation • Dynamic range extension • Single bunch intensities ~ 1010 e- • Multibunch “trains” (batches) up to 3x 20 bunches (2.8 ns), each ~ 0.7 1010 e- • Requires: selectable gain/attenuation (remotely!) • Commissioning, service, maintenance • Monitor supply voltages, LO-levels, temperatures, etc. • Requires: remote read-out for each downconverter. • Calibration signals • Long term offset control, due to temperature drifts, etc. • Automatic online calibration during BPM beam operation. • Requires: remote controlled calibration signals. Global Design Effort

  4. Goals for Nov/Dec 2007 Run • Commissioning/testing of an upgraded downconverter prototype module • 2 PCB’s each with 2 downmix channels (SLAC) • 1 PCB with controller circuit and calibration signal generation (Fermilab) • Installation of the new downconverter prototype in Nov/Dec 2007 • Testing of remote control and calibration functions using a “minimum” LabVIEW based test software (no EPICS integration at that time). • Focus on the downconverter, controller and calibration hardware to freeze the prototype design. • Beam tests may include other BPM improvements (software, etc.) and beam studies (TbT coupling correction) Global Design Effort

  5. Beam Position Signal Processing Magnitude-based processing of 4 separate BPM signals Down Mix A “Echotek” digital signal processing: LPF BPF up B A Down Mix B LPF BPF out in Down Mix C 1D polynomial fit: LPF C BPF D down Down Mix D 0.1 dB gain error ≡ 27 µm offset error ! LPF BPF Global Design Effort

  6. Calibration Scheme Down Mix B • 2 calibration tones: • 714 + ε MHz • 714 – ε MHz • In passband of the downconverter • Coupling through the button BPM • On-line calibration • In presents of beam signals • Available only in narrowband mode • Using separate Graychip channels LPF BPF Down Mix A LPF BPF Down Mix D LPF BPF Down Mix C LPF BPF ~ ~ PLL PLL 714 – 714 + Global Design Effort

  7. CAN Fieldbus Wiring • CAN fieldbus control: • PMC-CAN controller • Daisy chain up to 32 nodes • Differential signals, up to 125kBit/sec (@500 m length) Motorola 5500 in VME Crate CAN DB-9 CAN PMC-ECAN-2 124Ω Term resistor jumpered in on last board Twisted Pair Last BPM 1st BPM Twisted Pair CAN In CAN Out CAN In CAN Out DB-9 DB-9 DB-9 DB-9 CAN Transceiver PCA82C250 CAN Transceiver PCA82C250 CAN CAN MC9S12XEP100 uController MC9S12XEP100 uController Global Design Effort

  8. Block Diagram 2 1 2 2 1 4 3 2 2 3 Freq 1 LO Level Readout ADF4153 PLL ADF4153 PLL Cal ON/OFF Gain Control LNA on/off Temp Monitor PS Voltage Monitor SPI1 on/off load 12-Bit A/D VCO CAN0 SPI0 on/off load VCO VME crate/CAN Motorola 5500 w/PMC User Interface Service Building CAN Tunnel ~100’ Shielded Cat-5 ~30’ Shielded Cat-5 to next BPM XFORM TM01-02+ 714MHz +/- Buffers Regulator LP2989IM-3.0 Splitters Pads 3 VDC ADP-2-9 Regulator LP38692MP-5 To Couplers Near Pick-ups Freq 2 5 VDC 8VDC in Regulator LP38692MP-5 ADP-2-9 5VDC In Filter CLV0700E-LF 729MHz LO ÷8 ADF4007 1MB Flash (PLL freq settings) to SLAC 1st BPM Cal Box Freescale MC9S12XEP100 uController Global Design Effort

  9. Schematics: CAN Bus DRAFT Global Design Effort

  10. Schematics: CAL Board (µC & PLL) DRAFT Global Design Effort

  11. Schematics: Wiring Diagram DRAFT Global Design Effort

  12. Hardware Key Components • PMC-ECAN-2 Bus controller • Commercial PMC CAN bus controller • VxWorks PPC driver support • Freescale MC9S12XEP10016-bitµContoller • Serial interface support (CAN, I2C, RS485, etc.) • 8/10/12-bit ADC’s (2x16 ch.), timers, I/O, etc. • Up to 1M flash, 64k RAM, 4k EEPROM • Analog Devices AD4153 fractional PLL • Successfully tested the calibration generation during the last run (729 MHz locking, 714 ± ε MHz CAL signals). • Selectable frequency, on/off switch, acceptable phase noise and spurious harmonics. Global Design Effort

  13. Software Components Fermi Cal Box Fermi Cal Box Fermi Cal Box MC9S12XEP100 microcontroller control program MC9S12XEP100 microcontroller control program MC9S12XEP100 microcontroller control program CAN CAN SLAC Box • Code Warrior IDE for firmware development • No Operating system • USB/CAN programmable CAN PMC-ECAN-2 VxWorks CAN Driver (vendor) Fermi Cal Box command library VME Echotek BPM control and acquisition program VxWorks MVME5500 Global Design Effort

  14. Current Development Steps… • Hardware: • Finalization of the CAL board schematics • Ordering parts for a first prototype. • PCB layout. • Software & system integration • Waiting for CAN bus evaluation boards and software. • Integration of CAN bus controller software • µC firmware development to control PLL’s, logic level signals and read-out ADC’s. • Great help from JLab (Al Grippo): Code Warrior µC firmware Global Design Effort

  15. Open Questions • Hardware interface SLAC/Fermilab • Enclosure type and PCB dimensions? • Between PCB cabling and connectors? • Prototype “pre”-testing procedure • Integrated system test at Fermilab? • How? • Schedule? • ATF beam tests • Schedule? • Mechanical mounting of the new enclosures in the ring? • Power supplies and distribution? • CAN bus cabling? • Beam time? • Design review and preparing for quantity production! Global Design Effort

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