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Ongoing Computer Engineerin g Research Projects at the Lucian Blaga University of Sibiu Prof. Lucian VINTAN, PhD-Director Advanced Computer Architecture & Processing Systems Research Lab - http://acaps.ulbsibiu.ro/research.php The Research Team Prof. Lucian VINTAN, PhD – Research Chair

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Ongoing computer engineerin g research projects at the lucian blaga university of sibiu l.jpg

Ongoing Computer Engineering Research Projects at the Lucian Blaga University of Sibiu

Prof. Lucian VINTAN, PhD-Director

Advanced Computer Architecture & Processing Systems Research Lab - http://acaps.ulbsibiu.ro/research.php

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


The research team l.jpg
The Research Team

  • Prof. Lucian VINTAN, PhD – Research Chair

  • Assoc. Prof. Adrian FLOREA, PhD

  • Senior Lecturer Daniel MORARIU, PhD

  • Senior Lecturer Ion MIRONESCU, PhD

  • Lecturer Arpad GELLERT, PhD

  • Radu CRETULESCU, PhD student

  • Horia CALBOREAN, PhD student

  • Ciprian RADU, PhD student

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Computing hardware l.jpg
Computing hardware

14 Intel Compute nodes (2 processor HS21 blades with quad-core Intel Xeon)

2 Cell Compute nodes (2 processor QS22 blades withIBM PowerXCell 8i Processor )

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Our current research topics l.jpg
Our current research topics

  • Anticipatory Techniques in Advanced Processor Architectures

  • An Automatic Design Space Exploration Framework for Multicore Architecture Optimizations

  • Optimizing Application Mapping Algorithms for NoCs through a Unified Framework

  • Optimal Computer Architecture for CFD calculation

  • Adaptive Meta-classifiers for Text Documents

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Anticipatory techniques in advanced processor architectures l.jpg

Anticipatory Techniques in Advanced Processor Architectures

Prof. Lucian VINTAN, PhD

Assoc. Prof. Adrian FLOREA, PhD

Lecturer Arpad GELLERT, PhD

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Fetch bottleneck l.jpg
FetchBottleneck

  • Fetch Rateis limited by the basic-blocks’dimension (7-8 instructions in SPEC 2000);

    Solutions

  • Trace-Cache & Multiple (M-1) Branch Predictors;

  • Branch Prediction increases ILP by predicting branch directions and targets andspeculatively processing multiple basic-blocks in parallel;

  • As instruction issue width and the pipeline depth are getting higher, accurate branch prediction becomes more essential.

    Some Challenges

  • Identifying and solving some Difficult-to-Predict Branches (unbiased branches);

  • Helping the computer architect to better understand branches’ predictability and also if the predictor should be improved related to Difficult-to-Predict Branches.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Difficult to predict unbiased branches l.jpg
Difficult to predict unbiased branches

  • A difficult-to-predict branch in a certain dynamic context

    • unbiased

    • „highly shuffled“.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Predicting unbiased branches l.jpg
Predicting Unbiased Branches

  • State of the art branch predictors are unable to accurately predict unbiased branches;

    The problem:

  • Finding new relevant information that could reduce their entropy instead of developing new predictors;

    Challenge:

  • Adequately representing unbiased branches in the feature space!

  • Accurately Predicting Unbiased Branches is still an Open Problem!

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Slide9 l.jpg

Random DegreeMetrics

Based on:

  • Hidden Markov Model (HMM) – a strong method to evaluate the predictability of the sequences generated by unbiased branches;

  • Discrete entropy of the sequences generated by unbiased branches;

  • Compression rate (Gzip, Huffman) of the sequences generated by unbiased branches.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Issue bottleneck data flow l.jpg
Issue Bottleneck (Data-flow)

Conventional processing models are limited in their processing speed by the dynamic program’s critical path (Amdahl);

2 Solutions

  • Dynamic Instruction Reuse (DIR) is a non-speculative technique.

  • Value Prediction (VP) is a speculative technique.

    Common issue

  • Value locality

    Chalenges

  • Selective Instruction Reuse (MUL & DIV)

  • Selective Load Value Prediction (“Critical Loads”)

  • Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar / Simultaneous Multithreaded (SMT) Architecture to anticipate Long-Latency Instructions Results

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Exploiting selective instruction reuse and value prediction in a superscalar architecture l.jpg
Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture

Selective Instruction Reuse (MUL & DIV)

Selective Load Value Prediction (Critical Loads)

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Slide12 l.jpg

Selective Instruction Reuse and Value Prediction in in a Superscalar ArchitectureSimultaneous Multithreaded Architectures

Physical

Register

File

ROB

Fetch

Unit

Issue

Queue

Functional

Units

I-Cache

Decode

Branch

Predictor

Rename

Table

PC

RB

LSQ

D-Cache

LVPT

SMT Architecture (M-Sim) enhanced with per Thread RB and LVPT Structures

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Exploiting selective instruction reuse and value prediction in a superscalar architecture13 l.jpg

Power in a Superscalar Architecture

Estimation

Power Models

Hardware

Configuration

Cycle-Level

Performance

Simulator

Hardware Access Counts

Performance

Estimation

SPEC

Benchmark

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture

The M-SIM Simulator

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Slide14 l.jpg

Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture

Relative IPC speedup and relative energy-delay product gain with a Reuse Buffer of 1024 entries, the Trivial Operation Detector, and the Load Value Predictor

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Conclusions and further work l.jpg
Conclusions and Further Work in a

  • Indexing the SLVP table with the memory address instead of the instruction address (PC);

  • Exploiting an N-value locality instead of 1-value locality;

  • Generating the thermal maps for the optimal superscalar and SMT configurations (and, if necessary, developing a run-time thermal manager);

  • Understanding and exploiting instruction reuse and value prediction benefits in a multicore architecture.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Anticipatory multicore architectures l.jpg
Anticipatory multicore architectures in a

  • Anticipatory multicores would significantly reduce the pressure on the interconnection network performance/energy;

  • Value prediction, multithreading and the cache coherence/consistence mechanisms there are subtle, not well-understood relationships;

  • data consistency errors consistency violation detection and recovery;

  • The inconsistency cause: VP might execute out of order some dependent instructions;

  • Dynamic Instruction Reuse in a multicore system. Reuse Buffers coherence problemscache coherence mechanisms

  • Details at http://webspace.ulbsibiu.ro/lucian.vintan/html/#11

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


An automatic design space exploration framework for multicore architecture optimizations l.jpg

An Automatic Design Space Exploration Framework for Multicore Architecture Optimizations

Horia CALBOREAN, PhD student

Prof. Lucian VINTAN, PhD

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Multiobjective optimization l.jpg
Multiobjective optimization Multicore Architecture Optimizations

  • Number of (heterogeneous) cores in the processor becomes higher – the systems become more and more complex

  • More configurations have to be simulated

    (NP-hard problem)

  • Time needed to simulate all configurations prohibitive

  • Performance evaluation has become a multiobjective evaluation

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Solutions l.jpg
Solutions Multicore Architecture Optimizations

  • Reducing simulation time

    • parallel & distributed simulation

    • sampling simulation

  • Reducing number of simulations

    • intelligent multiobjective algorithms

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Proposed framework l.jpg
Proposed framework Multicore Architecture Optimizations

  • We developed FADSE (framework for automatic design space exploration)

  • Compatible with most of the existing simulators

  • Portable - implemented in java

  • Includes many well known multiobjective algorithms

  • Is able to run simulators and also well known test problems

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Existing tools l.jpg
Existing tools Multicore Architecture Optimizations

  • Bounded to a certain simulator (Magellan)

  • Lack portability - bounded to a certain operating system (M3Explorer, Magellan)

  • Perform design space exploration of small parts of the system (only the cache - Archexplorer)

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Fadse application architecture l.jpg
FADSE – application architecture Multicore Architecture Optimizations

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Features l.jpg
Features Multicore Architecture Optimizations

  • Parallel simulation (client server model)

  • Ability to introduce constrains through XML interface

  • Easily configurable through XML files:

    • change DSE algorithm,

    • specify input parameters and their possible values,

    • specify desired output metrics, etc.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Our target l.jpg
Our target Multicore Architecture Optimizations

  • Perform an evaluation of the existing algorithms on different simulators

  • Find out which one performs best

  • Improve the algorithms - map them on the specific problem of design space exploration

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Conclusions l.jpg
Conclusions Multicore Architecture Optimizations

  • We have developed a framework which is able to perform automatic design space exploration

  • Extensible, portable

  • Many implemented multiobjective algorithms (through the use of jMetal)

  • Reduces time through parallel &distributed execution of simulators

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Optimizing application mapping algorithms for nocs through a unified framework l.jpg

Optimizing Application Mapping Algorithms for NoCs through a Unified Framework

Ciprian RADU, PhD student

Prof. Lucian VINTAN, PhD

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Outline l.jpg
Outline Unified Framework

  • Introduction

    • The application mapping problem for NoCs

    • The relation between application mapping and routing

  • Evaluating application mapping algorithms for Networks-on-Chip

    • The framework design

    • The ns-3 NoC simulator

  • Automatic Design Space Exploration for Networks-on-Chip

    • The framework

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


The application mapping problem for nocs l.jpg
The application mapping problem for NoCs Unified Framework

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Application mapping routing l.jpg
Application mapping & routing Unified Framework

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Evaluating application mapping algorithms for networks on chip l.jpg
Evaluating application mapping algorithms for Networks-on-Chip

  • Existing application mapping algorithms are currently evaluated on specific NoCs

    • e.g.: NoCs with 2D mesh topology

  • Existing comparisons between the algorithms are not made on the same NoC architecture

  • We propose a unified framework for the evaluation and optimization of application mapping algorithms on different NoC designs

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


The framework design l.jpg
The framework design Networks-on-Chip

  • 3 major components:

    • A module that contains the implementation of different application mapping algorithms;

    • A network traffic generator;

    • A Network-on-Chip simulator.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


The framework design flow l.jpg
The framework design flow Networks-on-Chip

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


The ns 3 noc simulator l.jpg
The ns-3 NoC simulator Networks-on-Chip

  • Based on ns-3, an event driven simulator for Internet systems

  • Aims for a good accuracy – speed trade-off

  • Flexible and scalable

  • Current parameters:

    • Packet size, packet injection rate, packet injection probability;

    • Buffer size;

    • Network size;

    • Switching mechanism (SAF, VCT, Wormhole);

    • Routing protocol (XY, YX, SLB, SO);

    • Network topology (2D mesh, Irvine mesh);

    • Traffic patterns (bit-complement, bit-reverse, matrix transpose, uniform random).

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Automatic design space exploration for networks on chip l.jpg
Automatic Design Space Exploration for Networks-on-Chip Networks-on-Chip

  • Motivation

    • There is no NoC suitable for all kinds of workload

    • There is an exponential number of possible NoC architectures

  • Exhaustive DSE is no longer suitable

  • Automatic DSE uses an heuristic driven exploration of the design space

    • Disadvantage: near-optimal solutions

    • Advantage: speed

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


The framework l.jpg

Design Space Exploration module Networks-on-Chip

Network-on-Chip simulator

Configure the simulator

Simulation results

The framework

  • Components:

    • DSE module

    • NoC simulator

  • The DSE module determines the parameters of the NoC architecture

    • Uses algorithms from Artificial Intelligence

  • The NoC simulator (ns-3 NoC) is automatically configured to simulate the network architecture determined by the DSE module

  • The simulation results (network performance) help the DSE module at generating a better NoC architecture

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Optimal computer ar c hitecture for cfd calculation l.jpg

Optimal computer Networks-on-Chiparchitecture for CFD calculation

Senior Lecturer Ion Dan MIRONESCU, PhD

Prof. Lucian VINTAN, PhD

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Practical aplication l.jpg
Practical aplication Networks-on-Chip

  • Modelling and simulation of multiscale, multicomponent, multiphase flow in complex geometry (ongoing projects) for :

    • optimisation of sugar crystalisation

    • prediction of the flow properties of polymer based dispers systems (starch and starch fractions, microbial polysacharides)

      HPC/CFD

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Goals l.jpg
Goals Networks-on-Chip

  • Speed-up of this application on the given architecture

  • Finding the optimal manycore architecture  for CFD application (e.g. NoC)

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Method lattice boltzmann l.jpg
Method Networks-on-Chip - Lattice Boltzmann

(Chirila,2010)

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


M ethod advantages l.jpg
M Networks-on-Chipethod advantages

  • easy discretization of complex geometry

  • easy incorporation of “multi” models

  • easy paralelisation

  • easy cupling to other scale models (Molecular Dynamics)

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Computational model l.jpg
Computational model Networks-on-Chip

COMPUTE

COMPUTE

COMPUTE

Ghost data

EXCHANGE

COMPUTE

COMPUTE

COMPUTE

Local Values

COMPUTE

COMPUTE

COMPUTE

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


General purpose manycore platform l.jpg
General-purpose manycore platform Networks-on-Chip

What can be used and what must be accounted for:

  • ILP (super scalar, out of order, branch prediction)

  • Task and Thread LP (multicore/multiprocessor)

  • Mixed programming model (shared memory on blade, message passing between blades)

  • Cache system

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Special purpose many core platform l.jpg
Special purpose many core platform Networks-on-Chip

What can be used and what must be accounted for:

  • SIMD

  • Task and Thread LP (hardware multithreading, multicore/multiprocessor)

  • Message passing

  • Local store model –full user control

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Charm l.jpg
Charm++ Networks-on-Chip

  • provides a high-level abstraction of a parallel program

  • cooperating message-driven objects called chares

  • support for load balancing, fault tolerance, automatic checkpointing

  • support for all architectures trough a specific low level tier

  • NAMD MD implementd in charm++

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Charm lb implementation l.jpg
Charm++ LB implementation Networks-on-Chip

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Charm lb implementation46 l.jpg
Charm++ LB implementation Networks-on-Chip

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Slide47 l.jpg
DSE Networks-on-Chip

Search optimal values for

  • sites/bloc

  • blocs (chares)/core, /thread, /blade

  • communication patterns

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Slide48 l.jpg

Adaptive Meta-classifiers for Text Documents Networks-on-Chip

Prof. Lucian VINTAN, PhD

Daniel MORARIU, PhD

Radu CRETULESCU, PhD student

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Introduction l.jpg
Introduction Networks-on-Chip

  • We investigated a way to create a new adaptive meta-classifier for classifying text documents in order to increase the classification accuracy.

  • During the first processing phase (pre-classification) the meta-classifier uses a non-adaptive selector.

  • In the second phase (classification) we use a feed-forward neural network based on the back-propagation learning method.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


The architecture of the adaptive meta classifier m bp l.jpg
The architecture of the adaptive meta-classifier M-BP Networks-on-Chip

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Classification accuracy l.jpg
Classification accuracy Networks-on-Chip

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Time necessary for reaching the given total error l.jpg
Time necessary for reaching the given total error Networks-on-Chip

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Conclusions53 l.jpg
Conclusions Networks-on-Chip

  • This new adaptive meta-classifier uses 8 types of SVM classifiers and one Naïve Bayes type classifier to achieve the transposition of the input data from a large-scale space into a much smaller size space.

  • The best results (99.74% in terms of classification accuracy) were obtained using a neural network with 192 neurons in the hidden layer.

  • The meta-classifier managed to exceed the maximum "theoretical" limit of 98.63% which could be reached by an ideal non-adaptive meta-classifier that always chose the correct prediction if at least one classifier provide it.

  • For Reuters2000 text documents we obtained classification accuracy up to 99.74%.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


Some refererences computer architectures l.jpg
Some Refererences Networks-on-Chip – Computer Architectures

  • L. VINTAN, A. GELLERT, A. FLOREA, M. OANCEA, C. EGAN – Understanding Prediction Limits through Unbiased Branches, Eleventh Asia-Pacific Computer Systems Architecture Conference, Shanghai 6-8th, September, 2006 - http://webspace.ulbsibiu.ro/lucian.vintan/html/LNCS.pdf

  • A. GELLERT, A. FLOREA, M. VINTAN, C. EGAN, L. VINTAN - Unbiased Branches: An Open Problem, The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007), Seoul, Korea, August 23-25th, 2007 - http://webspace.ulbsibiu.ro/lucian.vintan/html/acsac2007.pdf

  • VINTAN L. N., FLOREA A., GELLERT A. – Random Degrees of Unbiased Branches, Proceedings of The Romanian Academy, Series A: Mathematics, Physics, Technical Sciences, Information Science, Volume 9, Number 3, pp. 259 - 268, Bucharest, 2008 - http://www.academiaromana.ro/sectii2002/proceedings/doc2008-3/13-Vintan.pdf

  • A. GELLERT, A. FLOREA, L. VINTAN. - Exploiting Selective Instruction Reuse and Value Prediction in a Superscalar Architecture, Journal of Systems Architecture, vol. 55, issues 3, pp. 188-195, ISSN 1383-7621, Elsevier, 2009 - http://webspace.ulbsibiu.ro/lucian.vintan/html/jsa2009.pdf

  • GELLERT A., PALERMO G., ZACCARIA V., FLOREA A., VINTAN L., SILVANO C. - Energy-Performance Design Space Exploration in SMT Architectures Exploiting Selective Load Value Predictions, Design, Automation & Test in Europe International Conference (DATE 2010), March 8-12, 2010, Dresden, Germany - http://webspace.ulbsibiu.ro/lucian.vintan/html/Date_2010.pdf

  • CALBOREAN H., VINTAN L. - An Automatic Design Space Exploration Framework for Multicore Architecture Optimizations, Proceedings of The 9-th IEEE RoEduNet International Conference, ISBN , Sibiu, June 24-26, 2010 - http://roedu2010.ulbsibiu.ro/ (indexata IEEE Xplore Digital Library)

  • RADU C., VINTAN L. - Optimizing Application Mapping Algorithms for NoCs through a Unified Framework, Proceedings of The 9-th IEEE RoEduNet International Conference, ISBN , Sibiu, June 24-26, 2010 - http://roedu2010.ulbsibiu.ro/ (indexata IEEE Xplore Digital Library)

  • L. N. VINTAN - Direcţii de cercetare în domeniul sistemelor multicore / Main Challenges in Multicore Architecture Research, Revista Romana de Informatica si Automatica, ISSN: 1220-1758, ICI Bucuresti, vol. 19, nr. 3, 2009, v. http://www.ici.ro/RRIA/ria2009_3/index.html

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


References 1 2 cfd calculation l.jpg
References (1/2) Networks-on-Chip - CFD Calculation

  • J. Hu and R. Marculescu, “Energy-aware mapping for tile-based NoCarchitectures under performance constraints,” inProceedings of the 2003Asia and South Pacific Design Automation Conference. Kitakyushu,Japan: ACM, 2003, pp. 233–239.

  • R. Marculescu and J. Hu, “Energy- and performance-aware mappingfor regular NoC architectures,” IEEE Transactionson ComputerAidedDesign of Integrated Circuits and Systems, vol. 24, no. 4, pp. 551–562,2005.

  • S. Murali and G. D. Micheli, “Bandwidth-Constrained mapping of coresonto NoC architectures,” inProceedings of the conference on Design,Automation and Test in Europe - Volume 2. IEEE ComputerSociety,2004, p. 20896.

  • K. Srinivasan and K. S. Chatha, “A technique for low energy mappingand routing in network-on-chip architectures,” in Proceedings of the2005 international symposium on Low power electronics and design.San Diego, CA, USA: ACM, 2005, pp. 387–392.

  • G. Ascia, V. Catania, and M. Palesi, “Multi-objective mapping for mesh-based NoC architectures,” in Proceedings of the 2nd IEEE/ACM/IFIPinternational conference onHardware/software codesign and systemsynthesis. Stockholm, Sweden: ACM, 2004,pp. 182–187.

  • J. P. Soininen and T. Salminen, “Evaluating application mapping usingnetwork simulation,” Proc of the Inter Symp on SystemonChip, vol. 1100,no. Kaitovyl 1, p. 2730,2003.

  • (2010) The SystemC website. [Online]. Available: http://www.systemc.org

  • S. Murali and G. D. Micheli, “SUNMAP: a tool for automatic topologyselection and generation for NoCs,” in Proceedings of the 41st annualDesign Automation Conference. San Diego, CA, USA: ACM, 2004,pp. 914–919.

  • C. Grecu, A. Ivanov, P.Pande, A. Jantsch, E. Salminen, U.Ogras,and R. Marculescu,“Towards open Network-on-Chip benchmarks,” inProceedings of the First International Symposium on Networks-on-Chip.IEEE Computer Society, 2007, p. 205.

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


References 2 2 cfd calculation l.jpg
References (2/2) Networks-on-Chip - CFD Calculation

  • S. Mahadevan, F. Angiolini, M. Storgaard, R. G. Olsen, J. Sparso, andJ. Madsen, “A network traffic generator model for fast Network-on-Chipsimulation,” in Proceedings of the conference on Design, Automationand Test in Europe - Volume 2. IEEE Computer Society, 2005, pp.780–785.

  • R. P. Dick, D. L. Rhodes, and W. Wolf, “TGFF: task graphs for free,”in Proceedings of the 6th international workshop on Hardware/softwarecodesign. Seattle, Washington, United States: IEEE Computer Society,1998, pp. 97–101.

  • (2010) The Embedded System Synthesis Benchmarks Suite (E3S)website. [Online]. Available:http://ziyang.eecs.umich.edu/~dickrp/e3s/

  • (2010) The Embedded Microprocessor Benchmark Consortium(EEMBC) website. [Online]. Available: http://www.eembc.org

  • (2010) The ns-3 network simulator website. [Online]. Available:http://www.nsnam.org/

  • H. vom Lehn, K. Wehrle, and E. Weing¨artner, “A performance comparison of recent network simulators,” 2009 IEEE InternationalConferenceon Communications, pp. 1–5, 2009.

  • S. Schlingmann, “Selbstoptimierendes routing in einem network-on-a-chip,” Master’s thesis, University of Augsburg,2007.

  • J. Duato, S. Yalamanchili, and L. M. Ni, Interconnection Networks: AnEngineering Approach, 1st ed. Institute ofElectrical & ElectronicsEnginee, 1997.

  • S. E. Lee and N. Bagherzadeh, “Increasing the throughput of anadaptive router in network-on-chip (NoC),” in Proceedings of the 4thinternational conference on Hardware/software codesign and systemsynthesis. Seoul, Korea: ACM, 2006, pp. 82–87.

  • E. Salmien, A. Kulmala, and T. D. Hamalainen, “Surveyof network-on-chip proposals,” White paper, © OCP-IP, Tampere University of Technology, March 2008. [On-line]. Available: http://ocpip.biz/uploads/documents/OCP-IP_Survey_of_NoC_Proposals_White_Paper_April_2008.pdf

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


References meta classifiers for text documents l.jpg
References - Meta-classifiers for Text Documents Networks-on-Chip

  • CRETULESCU R., MORARIU D., VINTAN L. – Eurovision-like weighted Non-Adaptive Meta-classifier for Text Documents, Proceedings of the 8th RoEduNet IEEE International Conference Networking in Education and Research, pp. 145-150, ISBN 978-606-8085-15-9, Galati, December 2009 (indexata ISI Web of Science - http://apps.isiknowledge.com/)

  • MORARIU D., CRETULESCU R., VINTAN L. – Improving a SVM Meta-classifier for Text Documents by using Naïve Bayes, International Journal of Computers, Communications & Control (IJCCC), Agora University Editing House - CCC Publications, ISSN 1841 – 9836, E-ISSN 1841-9844, Vol. V, No. 3, pp. 351-361, 2010

  • CRETULESCU R., MORARIU D., VINTAN L., COMAN I. D. – An Adaptive Meta-classifier for Text Documents, The 16th International Conference on Information Systems Analysis and Synthesis: ISAS 2010, Orlando Florida, USA, April 6th – 9th 2010

Advanced Computer Architecture & Processing Systems Research Lab

http://acaps.ulbsibiu.ro/research.php


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