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Basic Logic Gates. Discussion D5.1 Section 8.6.2 Sections 13-3, 13-4. Basic Logic Gates and Basic Digital Design. NOT, AND, and OR Gates NAND and NOR Gates DeMorgan’s Theorem Exclusive-OR (XOR) Gate Multiple-input Gates. NOT Gate -- Inverter. Y. X. 0 1. 1 0. NOT.

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Basic Logic Gates and Basic Digital Design

Basic Logic Gates and Basic Digital Design

Basic Logic Gates and Basic Digital Design

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

NOT

- Y = ~X (Verilog)
- Y = !X (ABEL)
- Y = not X (VHDL)
- Y = X’
- Y = X
- Y = X (textook)
- not(Y,X) (Verilog)

OR

- X | Y (Verilog)
- X # Y (ABEL)
- X or Y (VHDL)
- X + Y (textbook)
- X V Y
- X U Y
- or(Z,X,Y) (Verilog)

Basic Logic Gates and Basic Digital Design

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

Basic Logic Gates and Basic Digital Design

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

NAND Gate

X

Z

X

Z

=

Y

Y

Z = ~(X & Y)

Z = ~X | ~Y

X Y W Z

0 0 0 1

0 1 0 1

1 0 0 1

1 1 1 0

X Y ~X ~Y Z

0 0 1 1 1

0 1 1 0 1

1 0 0 1 1

1 1 0 0 0

NOR Gate

X

X

Z

Z

Y

Y

Z = ~(X | Y)

Z = ~X & ~Y

X Y Z

0 0 1

0 1 0

1 0 0

1 1 0

X Y ~X ~Y Z

0 0 1 1 1

0 1 1 0 0

1 0 0 1 0

1 1 0 0 0

De Morgan’s Theorem

- NOT all variables
- Change & to | and | to &
- NOT the result
- --------------------------------------------
- ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y)
- ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y
- ~X & !Y = ~(~~X | ~~Y) = ~(X | Y)
- ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

XOR

- X ^ Y (Verilog)
- X $ Y (ABEL)
- X @ Y
- xor(Z,X,Y) (Verilog)

XNOR

- X ~^ Y (Verilog)
- !(X $ Y) (ABEL)
- X @ Y
- xnor(Z,X,Y) (Verilog)

- NOT, AND, and OR Gates
- NAND and NOR Gates
- DeMorgan’s Theorem
- Exclusive-OR (XOR) Gate
- Multiple-input Gates

Multiple-input AND Gate

Z

1

Output is HIGH only if all inputs are HIGH

Z

1

An open input will float HIGH

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