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Technion  Israel institute of technology department of Electrical Engineering . High speed digital systems laboratory. Sub  Nyquist Sampling DSP & Support Change Detector Final Presentation. Performed by: Omer Kiselov Daniel Primor. : Supervised by
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Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Sub Nyquist Sampling DSP & Support Change DetectorFinal Presentation
Performed by:
OmerKiselov Daniel Primor
:Supervised by
Moshe Mishali Inna Rivkin
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
CTF
(Support recovery)
Analog
Backend
(Realtime)
DSP
(Baseband)
Expand
1:q
Memory
Detector
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
The Main Objective
SUPPORT GENERATION
DSP
(Baseband)
FIFO FOR
DELAY
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
DSP & SUPPORT CHANGE DETECTOR
A matrix vector 432 bits
Reconstructed samples
432 bits
Support Anlysis vector
101 bits
Valid samples 1 bit
Support Changed
1 bit
First Beta
(For QR decomposition)
36 bits
A Matrix Address 9 bits
Samples Bundle 432 bits
Valid Supports 1 bit
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
DSP & SUPPORT CHANGE DETECTOR BLOCK
Pseudo inverse
Real Time Vector Multiplier
Support Change Detector
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Pseudo inverse
Pseudo inverse
Real Time Vector Multiplier
Support Change Detector
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Pseudo inverse
QR Decomposition
Inverting an upper triangular matrix
Matrix Multiplier
QR Decomposition
Matrix Multiplier
Matrix Inversion
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
QR Decomposition
Inverting an upper triangular matrix
Matrix Multiplier
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Phase 2
Phase 1
Aux1
Aux2
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
for k = 1:n1
v = ones(n+1k,1);
if(k<o)
v(2:n+1k) = A(k+1:n,k);
end
Qk = eye(n);
Qk(k:n,k:n) = eye(n+1k)  (2/(v'*v))*(v*v');
Q = Qk*Q;
end
[n,m] = size(A);
for k = 1:min(n1,m)
v(k:n,1) = aux1(A(k:n,k));
A(k:n,k:m) = aux2(A(k:n,k:m),v(k:n,1));
A(k+1:n,k) = v(k+1:n,1);
end
Phase 2
Phase 1
B=Phase1(Acore);
Qtranse=phase2(B);
Rm=Qtranse*Acore;
Qm=Qtranse';
if (a(1) >= 0) beta = a(1) + norm(a);
else beta = a(1)  norm(a);
end
v(2:n) = 1/beta * v(2:n);
v(1) = 1;
Aux1
Aux2
beta = 2/(v'*v);
w = v'*A
A = A + beta*v*w;
Phase 2
Phase 1
Aux 2
Beta calculation unit
24 Multipliers
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Phase 2+Aux1/2
Phase 1+Aux1/2
ALUTs: 1300
Registers :10
ALUTs: 2500
Registers : 450
Block Memory bits 10000
Beta_calc
ALUTs: 1900
Registers :550
DSP block: 26
24_mults
ALUTs: 850
DSP block: 48
24 mults block + beta calc
Aux2
ALUTs: 1500
Registers :10
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
QR Decomposition
Inverting an upper triangular matrix
Matrix Multiplier
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Matrix Inversion Unit
Matrix Inversion Unit
Vector Inversion Unit
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
The Vector inverse runs on a faster clock – this work clock is a speed of 2 or three times the main clock (more if possible.
Since the multipliers only work at the rate of 50 MHz .There is also a division unit which works in 20 MHz frequency at the most.
Resources: 7000 ALUTs
880 registers
26 DSP blocks (18 bit multipliers)
for(m=1:s(2))
for(n=1:(m1))
for(k=1:(m1))
Rinv(n,m)=Rinv(n,m)+Rinv(n,k)*R(k,m);
end
end
for(w=1:(m1))
Rinv(w,m)=Rinv(w,m)/R(m,m);
end
if(R(m,m)~=0)
Rinv(m,m)=1/R(m,m);
end
end
end
Matrix Inverse:
Unit holds:
14000 memory bits
12500 registers
10000 ALUTs
30 DSP Blocks
Matrix Inversion Unit
Vector Inversion Unit
FIFO for Original R Matrix
Vector Inverter
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Matrix Inversion Unit
Matrix Multiplier
Matrix Multiplier’s Interface
QR Decomposition
Inverting an upper triangular matrix
Vector
Multiplier
Matrix Multiplier
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Matrix Multiplier’s Interface
a block for deciding what matrix goes where – since the multiplier is being
used by all blocks.
Resources for the whole block:
ALUTs: 60000
Memory bits : 30000
Registers : 11000
380 DSP blocks
Matrix Multiplier
Vector
Multiplier
RAM
Matrix Multiplier
Matrix Multiplier
Vector Multiplier
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
DSP
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Pseudo Inverse Resources
Pseudo inverse
Pseudo inverse
resources:
ALUTs: 80000
Memory bits : 60000
Registers : 30000
450 DSP blocks

<1%
=34%
=50%
Real Time Vector Multiplier
Support Change Detector
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Real Time Multiplier
Pseudo inverse
Real Time Vector Multiplier

<1%
<1%
=42%
Support Change Detector
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Support Change Detector
Pseudo inverse
Support Change Detector
Real Time Vector Multiplier
Support Change Detector
Support Change Detector
Technion  Israel institute of technology
department of Electrical Engineering
High speed digital systems laboratory
Full System
TOP!
Total System Requirements:
ALUT’s : 75000
Memory bits 70000
Registers 30000
DSP Blocks 805
Pins : 1000
All hardware requirements given by Quartus during synthesis.
Pseudo inverse
EP3SE260
=60%
0.05%=
15%=
101%=

EP3SL110
=87%
0.1%=
34%=
91%=

Real Time Vector Multiplier
Support Change Detector
The pseudo inverse module completed the simulation.
The support vectors and A_S were taken from the matlab simulation.
Plus the samples Yn which were multiplied in the matlab with the matrix.
Pseudo inverse takes about 200,000 clock cycles dependent on the amount of supports.