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Mica, Mica2, MicaZ

Mica, Mica2, MicaZ. Katarzyna Bilinska Marcin Filo Rafal Krystowski Supervisor: Dr. Waltenegus Dargie. Agenda. Motivation Architecture MICA, MICA2, MICA z Sensing sub-system Operating system Communication phases Test of Mica Mica2. Motivation.

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Mica, Mica2, MicaZ

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  1. Mica, Mica2, MicaZ Katarzyna Bilinska Marcin Filo Rafal Krystowski Supervisor: Dr. Waltenegus Dargie

  2. Agenda • Motivation • Architecture MICA, MICA2, MICA z • Sensing sub-system • Operating system • Communication phases • Test of Mica Mica2

  3. Motivation • Elimination of human involvement in gathering information • Smart environment relies first and foremost on sensory data from the real world.

  4. What is Mica? Mica, responsible for -processing, -storage -power supply - sending data to base station Sensing board, responsible for -sensing Ref. 1

  5. Why mica? • Mica wireless platform serves as a foundation for the emerging possibilities. • Nearly a hundred research groups currently use Mica nodes • Mica is created with off-the-shelf hardware • Mica does not require use of predefined protocols (except Mica Z) Ref. 3

  6. System architecture

  7. Logical architecture RFCommunication Power management Processing Secondarystorage I/OSub-system

  8. Logical architecture RFCommunication Powermanagement Processing Secondarystorage I/OSub-system

  9. Processing sub-system • Functions • Application execution • Resource management • Peripherial interaction

  10. Limited program space In Mica works at 4 MHz Processing Sub-System: Mica • Atmel AVR Atmega 103L (MCU) • 121 Instructions - Most Single Clock Cycle Execution • Up to 6 MIPS Throughput at 6MHz • 128k Bytes of In-System Programmable Flash • 4K Bytes Internal SRAM • 4K Bytes of In-System Programmable EEPROM • 53 Programmable I/O Lines • 3 hardware timers, 1 external UART, 1 SPI port • Atmel AVR AT90S2313 coprocessor • 8-pin flash-based microcontroler with an internal system clock • 5 programmable I/O Lines • Maxim DS2401 (silicon serial number) • Low cost ROM device • Unique, factory-lasered and tested 64-bit registration number guaranteed no two parts alike • No power requirements (no need for an external power source) • Minimal electronic interface (typically a single port pin of a microcontroller) Used to load the programme into main processor Used to identify Mica

  11. In Mica2,MicaZ works at 7,4 MHz No need of coprocessor Processing Sub-System: Mica2, MicaZ • Atmel AVR Atmega 128L (MCU) • 133 Instructions - Most Single Clock Cycle Execution • Up to 16 MIPS Throughput at 16MHz • 128k Bytes of In-System Programmable Flash • 4K Bytes Internal SRAM • 4K Bytes of In-System Programmable EEPROM • 53 Programmable I/O Lines • 3 hardware timers, 2 external UART, 1 SPI port • self reprogramable • hardware multiplier • JTAG debugging support (real-time, in-system debugging) • Maxim DS2401 (silicon serial number) • Low cost ROM device • Unique, factory-lasered and tested 64-bit registration number guaranteed no two parts alike • No power requirements (no need for an external power source) • Minimal electronic interface (typically a single port pin of a microcontroller) No need in MicaZ

  12. Logical architecture RFCommunication Powermanagement Processing Secondarystorage I/OSub-system

  13. I/O Sub-System • Functions • Interface with sensing boards • Interface with programming boards • Program and communicate with other devices

  14. expansion connector I/O Sub-System • The I/O subsystem interface consists of a 51-pin expansion connector • eight analog lines, • eight power control lines, • three pulse-width-modulated lines, • two analog compare lines, • four external interrupt lines, • an I2C-bus from Philips Semiconductor, • an SPI bus, • a serial port, • a collection of lines dedicated to programming the microcontrollers. Ref. 3

  15. Logical architecture RFCommunication Powermanagement Processing Secondarystorage I/OSub-system

  16. Secondary storage Sub-System • Functions • stores sensor data logs • temporarily holds program images received over the network interface

  17. Secondary storage Sub-System • 4 Mb (512 kB) memory organized as 2048 pages of 264 bytes each • Single 2.5V - 3.6V or 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible • 20 MHz Max Clock Frequency • Two 264-byte SRAM Data Buffers – Allows Receiving of Data while Reprogramming the Flash Memory Array • Low Power consumption – 4 mA Active Read Current Typical – 2 μA CMOS Standby Current Typical AT45DB041B

  18. Logical architecture RFCommunication Powermanagement Processing Secondarystorage I/OSub-system

  19. Power management Sub-System • Functions • regulate the system’s supply voltage

  20. Power management Sub-System (Mica) • Maxim1678 DC-DC converter provides a constant 3.0V supply 3 V • A solid 3V supply is required for radio operation • Lower voltage can be used to conserve energy when the radio is not in use • Battery produces energy between 3.2V and 2.0V • In an alkaline battery more than 50% energy lies below 1.2 V • Converter takes input voltage down to 0.8V and boosts it to 3.0V Ref. 3

  21. Power management Sub-System (Mica2/Z) • LM 4041 (precision voltage reference ) • Calibrate the battery voltage

  22. Logical architecture RFCommunication Powermanagement Processing Secondarystorage I/OSub-system

  23. Communication Sub-System • Functions • Transmit and receive data wirelessly • Coordinate with other nodes

  24. Communication Sub-Systemimplementation MICA • Radio TR 1000 • modulates-demodulates bit • Send data to processor bit by bit • AVR (Atmega 103L) • Protocol proccesing • Transmission power controler DS 1804 • Hardware accelerators • Serialization accelerator • Timing accelerator What is it? Why do we need them?

  25. M E M O R Y I/O B U S Application Controller Serialization Accelerator Timing Accelerator RF Transceiver Hardware Accelerators • I/O alone - recorded a maximum bandwidth of 10Kbps • I/O with hardware accelerators - we have been able to reach speeds of 50 Kbps Ref. 4

  26. Hardware Accelerators Overview We are using hardware accelerators for: SYNCHRONIZATION BIT TIMING BIT SAMPLING • each hardware accelerators has been built out of standard microcontroller functional units and rely on I/O programmed to detect start symbol Ref. 4

  27. Hardware Accelerators Timing Accelerator - automatically captures the exact timing of the edge transition of the timing pulse - incoming signal is automatically sampled every .25 us - detection of the start symbol gives us an indication of when the timing pulse will arrive - once the timing information is captured, software then uses it to configure a serialization accelerator that automatically times and samples the individual bits Ref. 4

  28. Hardware Accelerators Synchronization Accelerator -captures exact timing of incoming packet (within one clock cycle – 250ns) during the synchronization phase of packet reception -information available to application software Ref. 4

  29. Communication Sub-Systemimplementation MICA 2 • Radio CC1000 • Modulation demodulation • Hardware coding-decoding (Menchester) • Hardware synchronization • Send data to processor byte by byte • Power control • AVR(Atmega 128L) • Protocol processing No need of hardware accelerators No need of DS1804

  30. Communication Sub-Systemimplementation MICA z • Radio CC2420 (802.15.4 ZigBee) • Send data to processor in packets • Modulation, demodulation • Protocol processing • Synchronization • Coding, decoding • Error detection, corection • Acknowledgements No need of MCU in protocol processing

  31. Resistance to voltage supply variations- no need of DC-DC converter Communication

  32. Application controller Serialization accelerator Transm. Power Control Timing accelerator TR 1000 Radio sub-system architecture + Felxibility + Direct access to signal strength + Rich interface + Wide filed of decisions for programmist • -transmission speed limited by processor speed • - neccesity of low level programming

  33. Application controller CC 1000 Radio sub-system architecture • + hardware support for synchronization and coding/decoding • -limited flexibility

  34. Application controller CC2420 Radio sub-system architecture • lack of felxibility + easy to programme + 802.15.4 MAC hardware support + 802.15.4 MAC hardware security

  35. Architecture-summary

  36. Mica2 Architecture MicaZ Architecture Atmega 128 L CC2420 transceiver CC1000 radio transceiver Mica Architecture Ref. 3

  37. Sensing Sub-System

  38. Sensing Sub-System • Functions • Sampling physical signals/phenomena • Different types of sensors • Photo-sensor • Acoustic Microphone • Magnetometer • Accelerometer • Sensor Processor Interface • 51 Pin Connector • ON-OFF switches for individual sensors • Multiple data channels Ref. 1

  39. Other sensor boards • Ultrasonic transceiver – Localization • Used for ranging • Up to 2.5m range • 6cm accuracy • Dedicated microprocessor • 25kHz element • Basic Sensor board • Light (Photo), Temperature, Acceleration, Magnetometer, Microphone, Tone Detector, Sound Ref. 1

  40. Operating system

  41. Operating system • The Mica hardware platform has been designed to support the TinyOS execution model • TinyOS is an event based operating system • TinyOS allows for an application designer to select from a variety of system components in order to meet application specific goals.

  42. Communication phases

  43. RF Wakeup - it is necessary to put a collection of nodes to sleep for a long period of time - a radio signal is used to wake the nodes - RF based wake-up protocol - nodes have to periodically turn on the radio and check for wakeup signal Cost of checking = (radio on time) * (radio power consumption) -power consumption of the radio times the time the radios is on Power consumption = (checking frequency) * (cost of checking) -frequency of energy used each time it checks for the signal times the the check Avarage wakeup time = ½ (checking period) = 1/(2* checking frequency) -minimize the time a radio must be turned on each time a node checks for the wakeup signal -minimize the checking frequency Ref. 4

  44. Localization • RF localization : • - radio – additional sensor • - radio - analog sensor to detect the strength of an incoming signal • automatically determine the physical position of members • central controller can look at the signal strength of each individual bit as well as the level of the background noise • -sender helps the receiver determine the reception strength more accurately. Acoustic localization -an alternative to RF localization -more accurate Ref. 4

  45. Transmit command provides data and starts MAC protocol. Encode processing Start Symbol Transmission Preamble MAC Delay Transmitting encoded bits Bit Modulations Radio Samples Slow periodic sampling Receiving individual bits Synchronization Start Symbol Search Start Symbol Detecting Decode processing Wireless Communication Phases Transmission Data to be Transmitted Encoded data to be Transmitted Reception Encoded data received Data Received Ref. 4

  46. Test of Mica, Mica2

  47. Test of MICA, MICA2 Assumptions • measuring packet delivery rate • The nodes distributed in an ad-hoc manner Impact of the different conditions in the absence of interfering transmissions • Nodes placed in a variety of different positions • near the ground or elevated, • with or without LOS, • different levels of obstructions (furniture, walls,trees) • distances from 2 to 50 meters Mica 1 Mica 2 Ref. 2

  48. Test of MICA, MICA2 Experiment facts • 3 different Environments • Outdoor habitat reserve • Urban outdoor environment • Office building • 2 Radio type (TR1000, CC1000) • 6 different Transmission power settings • Mica from –10dBm to 0 dBm • Mica2 from –20dBm to +10 dBm • Packet size • 25, 50, 100, 150 and 200 bytes • up to 16 nodes in outdoor and up to 55 nodes in indoor experiments • packet delivery data from more than 300,000 packet probes • each node transmitting 200 packets Ref. 2

  49. packet packet packet packet packet MICA MICA MICA MICA MICA MICA Test of MICA, MICA2

  50. packet packet packet packet packet MICA MICA MICA MICA MICA MICA Test of MICA, MICA2

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