Microprocessors 1
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Microprocessors 1. History of Intel Processors. First microprocessor ~ Intel 4004 4-bit (nibble) data bus; contained 2000 transistors; 46 instructions; 4 KB of instruction code and 1KB of data Second generation (1974) ~ Intel 8008, 8080, 8085

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Microprocessors 1

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Microprocessors 1

Microprocessors 1


History of intel processors

History of Intel Processors

  • First microprocessor ~ Intel 4004

    • 4-bit (nibble) data bus; contained 2000 transistors; 46 instructions; 4 KB of instruction code and 1KB of data

  • Second generation (1974) ~ Intel 8008, 8080, 8085

    • 8-bit (byte) data bus; 8008 had a 14-bit address bus (16KB of memory); 8080 had a 16-bit address bus (64 KB of memory)

  • Third generation ~ Intel 8086

    • 16-bit data bus; backward compatible; used in the original IBM PC and IBM PC XT (eXtended Technology); 20-bit address

      (1 MB of memory); capable of handling 8 or 16 data bits at a time; 8088 is a stripped down 8-bit external data bus version


History of intel processors cont

History of Intel Processors cont…

  • 80286 (1982) was an improved architecture version used in the IBM PC AT (Advanced Technology)

  • 1985 ~ 80386DX

    • 32-bit data bus; backward compatible: could handle 8, 16, or 32-bits; 32-bit address bus (4 GB of memory); 80386SX is a stripped down 16-bit external data bus; 24-bit address bus (16 MB of memory)

  • 1989 ~ 80486DX

    Improved 80386DX with on-chip memory cache and math co-processor

    • 80486SX is an 80486DX with math-coprocessor link broken

    • Several versions: DX2-66 (33 MHz), DX2-50 (25 MHz), DX4-100 (25 MHz), DX4-75 (25 MHz)


  • History of intel processors cont1

    History of Intel Processors cont…

    • Pentium (P-5)

      • 64-bit ‘superscalar’ processor; can execute more than one instruction at time; 64-bit data bus; 32-bit address bus; twice as fast as equivalent 80486; improved floating-point operations; backward compatible.

    • Pentium II (P-6)

      Enhancement of the P-5; bus structure supports up to four processors; speeds >= 300 MHz; efficient power usage; P-6 bus detects and correct all single-bit and multi-bit bus errors.


    8086 and 8088 microprocessors

    8086 and 8088 microprocessors

    • 8086 has a 16-bit data bus; 8088 has an 8-bit external data bus

    • Both processors are constructed of DIP packages

    • Both are 5V processors:

      • 8086 draws a maximum supply current of 360 mA

      • 8088 draws a maximum supply current of 340 mA

      • 80C96/80C88 draw 10 mA

    • 8086: address bus pins AD0-AD15, A16/S3, A17/S4, A18/S5, A19/S6; data bus pins AD0-AD15

    • 8088: address bus pins AD0-AD7, A8-A15, A16/S3, A17/S4, A18/S5, A19/S6; data bus pins AD0-AD7


    Microprocessors 1

    Address is strobed from external latch (8282, 82C82) when ALE (Address Latch Enable) goes from high; data is latched when ALE pulses from low; ALE oscillates with regular clock cycle; the process of switching between data and addressing is called demultiplexing.


    8086 and 8088 microprocessors cont

    8086 and 8088 microprocessors – cont…

    • Input logic level: 0 = .8V, 1 = 2V

    • Output logic level: 0 = .45V, 1 = 2.4V

      Additional 8086/88 pins:

      • M/IO – indicates if address is memory or IO address

      • RD – when 0, data bus is driven by memory or an IO device

      • WR – microprocessor is driving data bus to memory an IO device. When 0, data bus contains valid data.

      • DT/R (data transmit/receive) – data bus is transmitting/receiving data

      • DEN (data bus enable) – activates external data bus buffers

    • Status (S0:S7) pin functionality:

      • S7:1, S6:0

      • S5: IF flag status

      • S4-S3: indicate which memory segment is being accessed


    8086 and 8088 microprocessors cont1

    8086 and 8088 microprocessors – cont…

    Status pin functionality- continued


    8086 and 8088 microprocessors cont2

    8086 and 8088 microprocessors – cont…

    Additional pin functionality:

    • INTR – when 1 and IF = 1, microprocessor prepares to service interrupt. INTA becomes active after current instruction completes.

    • INTA – Interrupt Acknowledge generated by the microprocessor in response to INTR. Causes the interrupt vector to be put onto the data bus.

    • NMI – Non Maskable Interrupt. Similar to INTR except IF flag bit is not consulted and interrupt is vector 2

    • CLK – clock input must have a duty cycle of 33% (high for 33.3%, low for 66.6%)


    Pin functionality cont

    Pin functionality cont…

    VCC/GND: power (5 and 0V)

    MN/MX: 0/1 ~ MIN or MAX mode

    BHE: Bus High Enable ~ enables the most significant data bus bits (D15-D8) during a read or write operation

    • READY – used to insert wait states (controlled by memory and IO for read/writes) into the microprocessor

    • RESET – microprocessor resets if this pin is held high for 4 clock periods. Instruction execution begins at FFFF0H and IF flag is cleared.

    • TEST – an input that is tested by the WAIT instruction. Commonly connected to the 8087 coprocessor


    Pin functionality cont1

    Pin functionality cont…

    • HOLD – requests a direct memory access (DMA). When 1, microprocessor stops and places address, data, and control bus in high-impedance state

    • HLDA (Hold Acknowledge) – indicates that the microprocessor has entered the hold state

    • R0/GT1 & R0/GT0 – request/grant pins used during maximum mode

    • Lock – lock peripherals off the system. Activated by using the LOCK: prefix on any instruction

    • QS1:QS0 – queue status bits show status of internal queue. Provided for 8087 access


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