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Agenda. Spartan ™ Philosophy Spartan-II FPGAs: Extending Spartan Series System Integration Spartan-II family: ASSP Replacement Summary. Philosophy behind Spartan™ Series. “Boldly go where no PLD has gone before” Expand PLD market to High Volume Segments Sampling of Target Markets:
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Agenda • Spartan™ Philosophy • Spartan-II FPGAs: Extending Spartan Series • System Integration • Spartan-II family: ASSP Replacement • Summary
Philosophy behind Spartan™ Series • “Boldly go where no PLD has gone before” • Expand PLD market to High Volume Segments • Sampling of Target Markets: • Digital Modems • DVD Players • Set-Top Box • Wireless Handsets • Computer Peripherals • Low Cost • Provide Density, Features, Performance at ASIC prices • Technology Enabler • Software and Cores enabling complex designs at very low cost, fast time to market
Lowering the Cost = Increasing Value High Performance System Features Software and cores Smallest Die Size Lowest Possible Cost Advanced Process Technology Leading FPGA Architectures Total Cost Management Low Cost Plastic Packages Streamlined Testing
Spartan-II: Extending Spartan Series More Gates More Performance 2X gates/$ 3X gates per I/O 2X I/O Performance 3X number of gates 100,000 Gates for $10 Feature Rich Time to Market DLLs Select I/O Block RAM Distributed RAM Cores Easy Design Flow Re-programmable Fast, Predictable Routing Reprogrammable ASIC/ASSP Replacement!
Higher Density Enables New Applications Spartan-III 350K $10 Spartan-II 100K Ethernet MAC Cable Modem System Gates Video Line Buffer Graphics Card Spartan-XL ATM IMA 40K Office Networking Reed Solomon Encoder Set-Top Box 64 Bit PCI Embedded mP Apps PCI-MIPS Bridge 30K 32-bit, 33-MHz PCI HDLC FIFOs UARTs PALs 1998 1999 2000 2001
Spartan-II Architecture CL DLL IOB IOB DLL CL . . . I/O Routing Ring I O B R A M CLB R A M I O B CLB . . . . . . I O B R A M R A M I O B . . . CLB CLB I/O Routing Ring CL DLL DLL CL IOB IOB Delay Lock Loop (DLL) Configurable Logic Block (CLB) Clock Management Multiply Clock Divide Clock De-skew Clock LOGIC and Distributed RAM Select IO Block Memory 4K bit Dual Port RAM 4Kx1 2Kx2 1Kx4 512x8 256x16 Power Management Sleep Mode Configuration and Register State Maintained
Spartan-II: High Volume System Integration PCI-MIPS System Controller $40 $7 $2 Dual Ports FIFOs Memory HSTL Translators $6 MIPS mP SSTL-3 Translators SDRAM $4 Clock Mgmt - Board deskew PLL $7.50 GTL+ Backplane Drivers PCI Master/ Target Controller $15 $6 QDR SRAMs SSTL3 2x CLK 5-volt tolerant I/O GTL+ PCI
ASIC & ASSP Market Data Consumer Portable Audio DVD Players PC Add-In Cards Communication Wireless Digital Modems Line Cards Data Processing Servers Laptops ASSP Consumer Communication ASIC Data Processing Data Processing Source: Dataquest
ASSP Replacement Dynamics Flexibility • Spartan FPGAs migrate to higher densities to handle system features • ASSP’s attempting to offer flexibility • Differentiation need due to market pressures • Changing system standards • PCI is the first successful ASSP competition ASSP System Features
A Successful Programmable ASSP XC2S100 FPGA PCI = 36 % of System Resources Estimated CY98 Revenue $M PCI IP The PCI IP from Xilinx is the most successful Programmable ASSP implemented to date
ASSP Replacement Addressable ASSP’s * ASSP’s currently unavailable * Xilinx Estimate
SpartanII Projected Pricing ,slowest speed/cheapest package (end CY2000)
Spartan-II Summary • Extends Spartan Series coverage into ASSP market • More gates per I/O and more gates per dollar • Higher density and performance • New features: Block RAM, DLL, Select I/O • Optimized for low cost and low power • Shipping Today Reprogrammability at ASIC prices 100,000 gates for $10
