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H-Cal SiPM ASIC Status

H-Cal SiPM ASIC Status. LAL Orsay S. Blin, J. Fleury, C. de la Taille, G. Martin, L. Raux. Contents. SiPM Readout Chip Reminder : chip Architecture Prototype Measurement: DAC performance Preamp+shaper CRRC2 Performance in Calibration Mode In Physics Mode Production Chip

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H-Cal SiPM ASIC Status

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  1. H-Cal SiPM ASIC Status LAL Orsay S. Blin, J. Fleury, C. de la Taille, G. Martin, L. Raux Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  2. Contents SiPM Readout Chip • Reminder : chip Architecture • Prototype Measurement: • DAC performance • Preamp+shaper CRRC2 Performance • in Calibration Mode • In Physics Mode • Production Chip • Chip Modifications • Production schedule • Production cost • Prospective Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  3. 40kΩ 100MΩ 0.1pF ASIC 2.4pF 8-bit DAC 0-5V 0.2pF 1.2pF 0.4pF 0.6pF 0.8pF 0.3pF in 12kΩ 4kΩ 24pF 10pF 10kΩ 50Ω 12pF 8pF 4pF 2pF 1pF 6pF 100nF 3pF Variable Gain Charge Preamplifier Variable Shaper CR-RC² Channel architecture for SiPM • 18-channel chip CMOS 0.8 µm • Compatible with ECAL read-out – Submitted in June 2004 – Received in September 2004 Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  4. Linearity DAC • Linearity 18 channels • 8 bit-DAC • Excursion 0-5V • Residuals DAC (V) CH0 in volts • Non linearity due to a mismatch in the current mirror Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  5. Noise vs DAC • SPE mode Cf=0.1 pF tau=12ns 1 SPE = 15 mV • DAC noise = Rf^2*(n*2qI+4kT/Rf) with Rf=50k and I=50µA = 300 nV/sqrt(Hz) (compared to 1.6 nV preamp) • Good agreement with (complete) simulations, but unsufficient filtering due to low DAC output impedance and too large series resistance to the filtering 100 nF • A factor ~1000 (=60dB) attenuation needed => low pass filter at 1kHz = 10 kohm*100nF The DAC has been redesigned to reduce the bandwidth and consequently its noise contribution Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  6. Chip modifications on DAC • Buffer on DAC and Read Register output 0.2pF CMOS switch 50kΩ Resistance added to filter DAC Noise I_mirror Preamp input 10kΩ OTA Rprot=50Ω 5pF 50Ω Capacitance added to have a better OTA stability Vref Unnecessarry resistance 100nF Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  7. MIP response • 1 MIP = 16 p.e. injected electronically (no detector) • Physics mode (left plot) : Vout = 30 – 40 mV tp = 150 – 180 ns • Calibration mode (right plot) tau = 24 ns Vout = 75 mV tp = 45 ns Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  8. Measurements results : MIP mode 200 ns • MIP electronic injection : 5 mV in 270pF (= 16 p.e. G = 1E6) • Dynamic range : ~ 80 MIPs (@ Cf=0.4pF) • Good agreement with simulations, but significant noise increase with DAC setting • *The injection capacitance has been increased from 5pF to 10pF • simulation done with the electronics injection (5mV in 270pF) Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  9. 0.5% -0.5% Linearity measurement (physics mode) • Cf=0.4pF ,Tau=200ns • Voltage swing : ~2.1V • Dynamic Range: [1-80 MIP] • Linearity<1% 80 MIP Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  10. Measurements results SPE mode • Single photoelectron response : 1 SPE = 0.16 pC • SPE electronic injection : 0.3 mV in 270pF Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  11. SiPM Connection • 1 SiPM connected with new biasing scheme • HV = 45 V +HV 8-bit DAC 100nF 100kΩ – Need 10k here SiPM input 50Ω ASIC 100nF Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  12. SPE spectrum • Cf=0.2pF, Tau=12ns pedestal Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  13. Schedule • Prototype Submission inJune 2004 • Prototype Delivery inSeptember 2004 • Test and validation with SiPM inOctober 2004 • Production (1000 chips) of the validated version with modifications on the DAC inNovember 2004 • Systematic test board Development in December 2004 • Production Delivery expected inJanuary 2005 • Systematic chips test inFebruary 2005 • Chips available for the collaboration byMarch-April 2005        Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  14. Production cost • Silicon : 1000 dies (area: ~10mm² ) 2 wafers needed:21.4 k Euros • Expected Production yield ~80% • Package : PQFP-100 :4.1 k Euros • Total :25.5 k Euros Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  15. Prospective and Conclusion • Chips available for the collaboration • Possible Development in 2005 chip of a Prototype in CMOS 0.35um • Prototype dedicated for SiPM: • Based on OPERA–ROC Chip Architecture: current conveyor • less noisy in Calibration Mode • Development of ADC to be embedded in the front-end chip Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  16. Measurements results : MIP mode 150 ns • Low noise mode : Rc short circuited • Dynamic range : ~ 80 MIPs (@ Cf=0.4pF) * The injection capacitance has been increased from 5pF to 10pF Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

  17. Measurements results SPE mode • Single photoelectron response : 1 SPE = 0.16 pC • SPE electronic injection : 0.3 mV in 270pF Ludovic Raux - Calice Meeting DESY - Mardi 7 décembre 2004

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