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MIGRATING FROM SDRAM TO DDR

MIGRATING FROM SDRAM TO DDR. Bill Gervasi Vice Chairman, JEDEC Memory Timing Technology Analyst bilge@transmeta.com. Topics to Cover. About JEDEC & DDR Market Segments & Fragments Design Architectures DDR Solutions Changes from SDR to DDR Timing Diagrams Impact to board design

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MIGRATING FROM SDRAM TO DDR

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  1. MIGRATING FROM SDRAM TO DDR Bill Gervasi Vice Chairman, JEDEC Memory Timing Technology Analyst bilge@transmeta.com

  2. Topics to Cover • About JEDEC & DDR • Market Segments & Fragments • Design Architectures • DDR Solutions • Changes from SDR to DDR • Timing Diagrams • Impact to board design • Why Not Rambus?

  3. About JEDEC & DDR • Setting open standards for >25 years • Consortium of 350 companies • Memory suppliers • Users from all market segments • Double Data Rate (DDR) SDRAM • Latest approved JEDEC standard • Results of collaborative market analysis

  4. Segments & Fragments Servers Workstations PC Segment 2 PC Segment 1 PC Segment 0 Mobile Graphics DDR PC100 PC133 PC100 PC133 DDR Rambus PC100 DDR Rambus PC100 PC133 DDR PC100 DDR PC133 PC66 PC100 DDR PC133 DDR SDRAM (x16) SS167 DDR SDRAM(x32) 2H99 1H00 2H00 1H01 2H01

  5. Market Factors • Server per-system memory capacity increasing faster than PC • Segments 1, 2 split Intel & non-Intel • UMA graphics takes over Segs 0 & 1 • “Sealed Box” PC for home market • Mobile market mostly skips PC-133 • DDR power lower than SDR • Graphics early: short design cycles

  6. RAM Evolution 3200MB/s MainstreamMemories DDR II 2100MB/s DDR 1000MB/s SDR 400MB/s Simple,incrementalsteps 320MB/s EDO FP

  7. Continued Tradition DDR is the logical incremental step • Performance enhancements • Detailed documentation • Full support from vendors & users

  8. System Designs PC/Server Memory Controller* Small Systems Controller * Single chip or separateclock, data & address chips • Point to point • 200MHz clock • 3.2GB/s transfer • Sockets & Stubs • 133MHz clock • 2.1GB/s transfer

  9. DDR Solutions PC/Server Applications Small Systems PC-266 Devices PC-2100 Modules 1-4 Slots Long traces, < 8” Termination No dummy modules SS-400 Devices Direct connect 2-8 DDR SDRAMs Short traces, < 2” No termination Built for speed

  10. How Different is DDR? • Simple upgrade to SDR designs • Similar PCB characteristics • Same fast RAS/CAS command set • A few evolutionary improvements • Bidirectional data strobe • Low voltage swing I/O • JEDEC Standards • Data sheet including IBIS curves • Module gerbers, application notes

  11. From SDR to DDR Signaling Clocks Pin Count Data Strobe Packages

  12. From SDR to DDR Signaling Clocks Pin Count Data Strobe Packages

  13. DDR Signaling • SSTL_2 low voltage swing inputs • 2.5V I/O with 1.25V reference voltage • Low voltage swing with termination • Rail to rail if unterminated

  14. From SDR to DDR Clocks Signaling Pin Count Data Strobe Packages

  15. DDR Clocks • Differential clocks on adjacent traces • Timing is relative to crosspoint • Helps insure 50% duty cycle

  16. “Slow” Signal Timing • Based on CK  • Loading mismatch,  single data rate • Addresses & Control signals

  17. From SDR to DDR Signaling Clocks Data Strobe Pin Count Packages

  18. “Fast” DDR Read Timing • Data valid on rising & falling edges • Source Synchronous: • Data Strobe “DQS” travels with data

  19. Read Timing 200MHz CK tDV insures worst case shift on DQS can’t happen(sufficient timing margin for system design!)

  20. A Totally Sync Design • Operate solely in memory clock timing domain • Fast design for small systems • Tight layout required

  21. “Fast” DDR Write Timing • DQS centered in data valid eye • DM timing & loading identical to DQ • Flexible to support large systems

  22. DDR Write Design Hint • Early DQS stresses back to back ops • Late stresses the array update •  1.0 * tCK is best “Perfect” alignmentat 1.0 * tCK Good solution forsingle chipcontrollers

  23. Emphasis on “Matched” • DM/DQS loading identical to DQ • Route as independent 8bit buses CONTROLLER DDR SDRAM DQ/DQS VREF VREF DM VREF VREF Disable

  24. 64 = 8 x 8 • 64bit bus is 8 sync’ed 8bit buses • Allows external “copper” flexibility • 8 buses resync upon entry to FIFO x16 DDRSDRAM x16 DDRSDRAM x16 DDRSDRAM x16 DDRSDRAM Copperfromcontrollerto SDRAMs 8 DQ1 DM1 DQS 8 DQ1 DM1 DQS 8 DQ1 DM1 DQS 8bit Buffer 8bit Buffer InsideController Sync toControllerclock 64bit Memory Controller Internal FIFO

  25. From SDR to DDR Signaling Clocks Pin Count Data Strobe Packages

  26. Packages • Device • 66pin TSOP same size as 54pin TSOP • Same 400x875mil, .65mm vs .80mm • DIMM • 184pin same size as 168pin • Same 5.25”, same pin pitch (key filled) • SO-DIMM • 200pin slightly longer than 144pin • 73mm vs. 68mm, .65mm vs. .80mm

  27. From SDR to DDR Signaling Clocks Pin Count Data Strobe Packages

  28. Pin Count Versus SDR • One DQS for 8 DQ (x8, x16 SD)--- or --- • One DQS for every 32 DQ (x32 SG) • One /CK adjacent to every CK • One VREF • Additional VDDQ, VSS? • DQ/DM/DQS:VDDQ:VSS ratio of 4:1:1 • Total: 5-12 more pins

  29. Combined SDR/DDR DDR • 2.5V I/O supply • Differential CK and CK • DQS for reads • Write latency one clock • CAS latency 2, 2.5, (3) • Series & parallel term’n • Burst length 2, 4, 8 • Reference voltage VREF SDR • 3.3V I/O supply • Single ended CLK • Echo CLK for reads • No write latency • CAS latency 2, 3 • Series termination • Burst length 1, 2, 4, 8 • No reference voltage • Combined SDR & DDR controller is a reasonable way to minimize risks

  30. Hints for the Future You’ll get the fastest designs if you: • Don’t use command interrupts • Don’t use autoprecharge • Fixed burst length 4 • Programmable drive impedance • Weak and strong drivers are standard • Unbroken ground planes & islands

  31. Why Not Rambus?

  32. Compare DDR & Rambus POWER COST PERFORMANCE

  33. DDRAdvantage $10+ royalties 15% 27% 33% 40% Reason Die, Heat sinks,dummy modules 28 ±10% vs.55 ±15% Packet protocol Frequency * width Frequency DDR Versus Rambus DIMM cost: PCB cost: Latency: Peak BW: Power: Email me to get the white paper detailing this analysis

  34. Rambus Market Issues • High latency • Poor fit for UMA graphics • High power • Poor fit for mobile • Costly materials • Poor fit for cost sensitive systems • Leaves the $2500+ PC market as a fit • Insufficient volumes to create a market • Other solutions needed anyway

  35. Summary • DDR is here today • Double the bandwidth • Evolutionary design change over SDR • Cheaper, faster, & cooler than Rambus • Applies to all market segments • Industry Standards • Detailed complete data sheet & models • Module designs on the web • Visit http://www.jedec.org

  36. Call to Action • Watch allthe market trends • Let your memory vendor know about your commitment to DDR • Let the trade press know your choice • Use smart engineering to push limits • Join JEDEC and influence the future

  37. Thank You

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