HOMEWORK 4-1. Compute the low and high noise margins using the following transfer curve of a Pseudo-pMOS inverter. HOMEWORK 4-2. The circuits below show different implementations of an inverter whose output is connected to a capacitor.
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a. Which one of the circuits consumes static power when the input is high?
b. Which one of the above circuits consumes static power when the input is low?
c. VOH of which circuit(s) is 1.2V?
d. VOL of which circuit(s) is 0V?
e. The proper functionality of which circuit(s) depends on the size of devices.
Calculate VOL, VOH，VIL，VIH，NML and NMH for a two-input NOR gate fabricated with CMOS technology.
(W/L)p= 4 (W/L)n= 1
VT,n=0.7V VT,p=-0.7V
μnCox=40uA/V2
μpCox=20uA/V2
VDD=5V
Design a resistive-load inverter with R=1KΩ, such that VOL=0.6V. The enhancement-type NMOS driver transistor has the following parameters:
VDD=5.0V VT0=1.0V
γ=0.2V1/2 λ=0
unCox=22.0uA/V2
Consider a CMOS inverter with the folloeing parameters:
nMOS VT0=0.6V unCox=60uA/V2 W/L=8
pMOS VT0=-0.7V upCox=25uA/V2 W/L=12
Calculate the noise margins and the switching threshold VTh of this circuit. The power supply voltage is VDD=3.3V.
Design a CMOS inverter circuit:
Use the device parameters as folloe:
nMOS VT0=0.6V unCox=60uA/V2
pMOS VT0=-0.7V upCox=25uA/V2
The power supply voltage is VDD=3.3V. The channel length of both transistors is Ln=Lp=0.8um.
For the conductor shown in the figure, calculate the capacitance of the conductor,
a. while the conductor area is in metal 1.
b. while the conductor area is in polysilicon.
c. while the conductor area is in n-diffusion layer.
一个CMOS反相器电路具有以下特性：
Cout=100 fF tdr=123.75 ps
Cout=115 fF tdr=138.60 ps
反相器是对称设计，kn=kp，VTn=│VTp│。
What is the primary reason for the reduction in the rise time at the output of the following circuit configurations ? Explain this classic CMOS trade-off (in one sentance).
x
Consider the circuit of the following figure.
a. What is the logic function implemented by the CMOS transistor network? Size the NMOS and PMOS devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 4
and PMOS W/L = 8.
b. What are the input patterns that give the worst case tpHLand tpLH. State clearly what are the initial input patterns and which input(s) has to make a transition in order to achieve this maximum propagation delay. Consider the effect of the capacitances at the internal nodes.
a. Do this two circuits implement the same logic function? If yes, what is that logic function? If no, give Boolean expressions for both circuits.
b. Will these two circuits’ output resistances always be equal to each other?
c. Will these two circuits’ rise and fall times always be equal to each other? Why or why not?