1 / 20

VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems

VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems. Pao-Ann Hsiung*, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, and Sao-Jie Chen *National Chung Cheng University Chiayi-621, Taiwan, R.O.C.

noreen
Download Presentation

VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems Pao-Ann Hsiung*, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, and Sao-Jie Chen *National Chung Cheng UniversityChiayi-621, Taiwan, R.O.C. The 5th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC’02), April 29~May 1, 2002, Washington D.C., USA

  2. Outline • Introduction • VERTAF Components • Application Development • AICC Cruise Controller Example • Conclusions & Future Work

  3. Introduction software components formal verification Portable Reusable Well-defined Interface Verifiable Correct Designs Model Checking Design Patterns Design Reuse Class Libraries Verifiable Embedded Real-Time ApplicationFramework(VERTAF) Integration of 3 Technologies:

  4. VERTAF Components

  5. VERTAF Components • Implanter: Autonomous Timed Objects (ATO) • Modeler: Autonomous Timed Processes (ATP) • Scheduler: Policy Selector, Schedule Generator • Verifier: Model Checker (TA+TCTL) • Generator: Code Generator

  6. Implanter • Implanter provides a standard OO interface for designer to input application domain objects • Autonomous Timed Object (ATO) • Interface • Port-Based Object (PBO), IEEE-TSE’97 • Not independent, shared memory communication • Method • Time-triggered Message-triggered Object (TMO), IEEE Computer’2000

  7. Autonomous Timed Object

  8. Modeler • Semantic model generation for ATO • Autonomous Timed Process (ATP) • Each ATP is associated with one ATO • An ATO may have several ATPs (use cases) • Two kinds of interrupts • Event Interrupt: execute an Event-Triggered Method • Timer Interrupt: execute a Time-Triggered Method • Check constraints after each iteration

  9. Autonomous Timed Process

  10. Call Graph & Process Table • Call Graph: call relationships among ATPs • schedulability test, resource allocation, scheduling, conflict resolution • Process Table: ATP + properties • resource allocation, scheduling, verification

  11. Scheduler • Policy Selector • User selects scheduling policy • Extended Quasi-Static Scheduling • Rate Monotonic • Earliest Deadline First • VERTAF automatically decides • Schedule Generator • Start / finish times for each ATP process • Priority Inversion Problem • Priority Inheritance Protocol

  12. Verifier • Formal Verification • Model Checking • System Model • ATP  Timed Automata or Petri Nets • Call Graph  Assume-Guarantee Reasoning • Property Specification • Timed Computation Tree Logic (TCTL) • Process Table, Call Graph, Schedules • Tool Kernel: State-Graph Manipulators (SGM) http://www.cs.ccu.edu.tw/~pahsiung/sgm/

  13. Model Checking Kernel from SGM Symbolic_Mcheck(S, ) Set of TA S; TCTL formula ; { Let Reach = Unvisited = {Rinit}; While (Unvisited NULL) { R = Dequeue(Unvisited); For all out-going transition e of R { R = Successor_Region(R, e); IfR is consistent & RReach { Reach = Reach {R}; Queue(R, Unvisited); } } } Label_Region(Reach, ); ReturnL(Rinit); }

  14. Generator • Code Architectures • With RTOS Multiple preemptive threads with synchronizations • Without RTOS Executive kernel using either polling or interrupt based architecture • Memory Bound Guaranteed by Extended Quasi-Static Scheduling • Timing Constraints: Guaranteed by Real-Time Schedulability Analysis • Code Optimality : Minimum Number of Tasks  small code size

  15. Application Development Specification Integration Generation

  16. Autonomous Intelligent Cruise Controller (AICC) Example Swedish Road Transport Informatics ProgrammeInstalled in a SAAB automobile

  17. # Task Description Object Period (ms) Execution Time (ms) Deadline 1 Traffic Light Info SRC 200 10 400 2 Speed Limit Info SRC 200 10 400 3 Proc. Vehicle Estimator ICCReg 100 8 100 4 Speed Sensor ICCReg 100 5 100 5 Distance Control ICCReg 100 15 100 6 Green Wave Control ICCReg 100 15 100 7 Speed Limit Control ICCReg 100 15 100 8 Coord. & Final Control FinalControl 50 20 50 9 Cruise Switches Supervisor 100 15 100 10 ICC Main Control Supervisor 100 20 100 11 Cruise Info Supervisor 100 20 100 12 Speed Actuator EST 50 5 50 AICC Example: Process Table SRC: Short Range Communication, ICCReg: ICC Regulator, EST: Electronic Servo Throttle

  18. AICC Example: Call-Graph SRC: Short Range Communication, ICCReg: ICC Regulator, EST: Electronic Servo Throttle

  19. Framework Evaluation Metric: Relative Design Effort NATO is the number of ATO, NAFO is the number of VERTAF objects, TWF is the design time with the framework, and TWOF is the design time without the framework. NATO = 5, NAFO = 21, TWF = 5 days, TWOF = 20 days AICC Example (Contd.) With VERTAF: you need only 4.8% effort

  20. Conclusions • Lesser Coding, Shorter Design Time • Verifiably Correct Software Designs • Automatic Code Generation • Current Work: RT-UML  Petri Nets or Timed Automata  Java or C code • Future Work: Larger Domain of Applications, Memory/Time Tradeoff

More Related