A 14-b 100-MS

1. A 14-b 100-MS/s Pipelined ADC With aMerged SHA and First MDAC Byung-Geun Lee, Member, IEEE, Byung-Moo Min, Senior Member, IEEE,Gabriele Manganaro, Senior Member, IEEE, and Jonathan W. Valvano, Member, IEEE Adviser : Hwi-Ming Wang Student : Wei-Guo Zhang Date : 2009/10/28

2. Outline Abstract Introduction Low-Power Techniques In Pipeline ADC Proposed Opamp And Capacitor Sharing Technique Circuit Implementation Measurement Results Conclusion References

3. Abstract This paper presents low-power 14-bit 100-MS/s ADC Further reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA) into the first multiplying digital-to-analog converter (MDAC) using the proposed opamp and capacitor sharing technique The ADC, implemented in a 0.18-um dual-gate-oxide(DGO) CMOS technology 72.4-dB SNDR, 88.5-dB SFDR 11.7 effective number of bits at full sampling rate 46-MHz input While consuming 230-mW from a 3-V supply

4. Introduction Mobile wireless communication systems are major applications of recent analog-to-digital converters (ADCs). In these applications, the specifications of the ADC vary significantly across different receiver architectures IF-sampling superheterodyne receivers require high-speed high-resolution ADCs, because intermediate frequency (IF) signals are directly converted to digital codes. Regardless of the receiver architectures, low-power consumption, and small die area are key specifications

5. Introduction

6. Introduction In this paper, the opamp-sharing technique is chosen for low-power and small area. A discharge phase is added to suppress memory effects. In addition, instead of removing the SHA, it is merged with the first MDAC. Thus, the ADC achieves low-power operation without compromising speed or accuracy

7. Low-Power Techniques In Pipeline ADC  A. Opamp-Sharing Technique(A conventional pipeline stage operates with a two-phase nonoverlapping clock)

8. Low-Power Techniques In Pipeline ADC Thus, significant power and area can be saved by reducing the number of opamps. It also has two drawbacks since the opamp is always active, there is no time to reset the opamp and the previous sample stored on the opamp input capacitance affects the current output This can be relaxed by using a feedback signal polarity inverting (FSPI) technique Is that it requires additional switches at the opamp input node to disconnect the opamp when it is not needed. These switches introduce series resistance and degrade the settling behavior

9. Low-Power Techniques In Pipeline ADC B. Switched-Opamp Technique Switched-opamp was first invented for low-supply operation Since the opamp does not need to be active during the sampling phase, it can be turned off. However, this requires the opamp to be turned on and off at each clock which limits the operating speed Recently, a partially switched-opamp technique was proposed to improve the settling behavior at the cost of power consumption. Unlike a conventional switched-opamp technique, the second stage of the two-stage opamp is turned off during the sampling phase(when the opamp is not needed).

10. Low-Power Techniques In Pipeline ADC C. Removing Front-End SHA In a typical pipelined ADC with opamp-sharing, the front-end SHA consumes about 20% to 30% of the total ADC power and often limits the linearity and dynamic range of the ADC. The concept of completely removing the SHA was first published for low-power operation in It has two drawbacks it requires a short comparison phase between the sampling and amplification phases of the first stage and an additional feedback capacitor decreases the feedback factor. Is an aperture error caused by resistance�capacitance (RC) delay mismatch between the input networks for the first multiplying digital to analog converter (MDAC) and the flash ADC

11. Proposed Opamp And Capacitor Sharing Technique Further power and area savings can be achieved by sharing both the opamp and the capacitors The idea behind the opamp and capacitor-sharing technique is that after the current stage generates the output, the charge on the feedback capacitor is reused for the following stage instead of being thrown away

12. Proposed Opamp And Capacitor Sharing Technique Opamp and capacitor-sharing technique.

13. Proposed Opamp And Capacitor Sharing Technique Two important facts need to be noted on this technique. First, the amplification phase is about 20% to 30% shorter than that of a conventional due to the addition of the discharge phase Using this technique, the total opamp load in amplification phase is reduced by about 40% to 60% depending on the architecture of the stage compared to that of a conventional one. The reduced output load allows the opamp output to settle faster to the required accuracy without increasing power. The second important fact relates to the memory effect However, since there is no reset phase between 1 and 2 , the stage i+1 has the memory effect. Thus,it is important to keep the error voltage caused by the memory effect small such that it does not affect the output of the stage i+1

14.  Circuit Implementation  In this prototype design, the SHA is completely merged with the first MDAC (SMDAC)

15. Circuit Implementation SMDAC works with three clock phases: sample/amplification (S/A), discharge and hold phases

16.  Circuit Implementation 

17. Circuit Implementation

18.  Measurement Results  The prototype ADC is implemented in 0.18- m DGO CMOS technology and occupies a die area of 7.28 (2.8*2.6 ). This includes the ADC core and the peripheral circuits such as bandgap, reference buffers,clock,SMDAC,digital error correction,5 opamp sharing stage&fadc.

19.  Measurement Results  The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 0.8 and 2.1 LSB, respectively

20.  Measurement Results 

21.  Measurement Results  Measured dynamic performance versus input and sampling frequency

22.  Measurement Results  The comparison of figure of merit (FOM). The ADC performance is summarized in Table I.

23.  Conclusion  A 14-b 100-MS/s ADC with low power consumption and small die area has been described In addition to sharing an opamp between two successive pipeline stages, the front-end SHA are completely merged into the first MDAC by using the proposed opamp and capacitor sharing technique The ADC achieves low power consumption and small die area while maintaining high-speed high-resolution operation

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