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Analytical Modeling of RF Noise in MOSFETs – A Review

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Analytical Modeling of RF Noise in MOSFETs – A Review

S. Asgaran and M. Jamal Deen

Electrical and Computer Engineering, CRL 226

McMaster University, Hamilton, ON L8S 4K1, Canada jamal@mcmaster.ca

- DUTs are fabricated in 0.18mm CMOS technology and measured at VDS = 1V
- Maximum fT is around 50 GHz and the best NFmin is about 0.5 dB at 2 GHz

distance

The battery life time and the distancebetween the wireless components will be limited by the noise floor of the front-end amplifier.

- Introduction
- Noise sources
- RF MOSFET noise models: long and short channel – only explicit analytical models are discussed
- Induced gate noise
- Applications of models to design
- Conclusions

- Why CMOS for RF?
- Low cost
- High integration
- Integration with digital IC (SoC)
- Technology advancement
- higher frequencies

J.C. Rudell, J-J. Ou, T.B. Cho, G. Chien, F. Brianti, J.A. Weldon, P.R. Gray, A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applicationsIEEE Journal of Solid-State Circuits, Vol. 32, pp. 2071-2088, Dec. 1997

SiD: Channel noise + flicker noise

SiG: Induced gate noise

SiR: Thermal noise of real resistances

SvRG

RG

G

CGS

CGB

SiG

CGD

Im

Ims

RD

RS

S

D

SiRS

SiD

SiRD

RDS

CBS

CBD

RDSB

SiRDSB

SiRSB

RSB

RDB

SiRDB

B

B

88%

0.25mm technology

SiD ~ Lch-1

RSUB ~20% total Sin

RG ~5% total Sin

L=0.18 mm, f=3 GHz

A.J. Scholten et al, Noise modeling for RF CMOS circuit simulation, IEEE Trans. Electron Devices, Vol. 50, pp. 618- 632, Mar. 2003.

C. Enz, An MOS transistor model for RF IC design valid in all regions of operation IEEE Trans. Microwave Theory Tech., Vol. 50, pp. 342-359, Jan. 2002.

~20% discrepancy for 0.18mm, low f

SiD increases with f in 2mm FET

No dependence on VDS in saturation

- Klaassen-Prins:
- Integrating the noise current over the entire channel

- Van der ziel:
- Includes hot electron effects
- Te: a function of E(x)

- Tsividis:
- Simpler model

20

VGS=0.7, 0.9, 1.1, 1.3, 1.9V

VDS=2.5V

16

12

G

iD (Amp/Hz1/2)

8

4

D

S

(I)

(II)

Lsat,VDSat

DL

0

0

2

4

6

8

10

12

Leff,VDS

Channel Length (mm)

- Increased noise in short channel devices
- A divided channel is used
- Linear region (GCA)
- Velocity saturation region; thermal assumption questionable

P. Klein, An analytical thermal noise model of deep submicron MOSFET’s, IEEE Electron Dev. Letters, Vol. 20, pp. 399-401, Aug. 1998.

vsat~107cm/s

t~4.3ps

SID ~ indep. of VDS

10-21

Measurement

Total noise

Region I noise

10-22

Drain Current Noise (Amp2/Hz)

Region II noise

10-23

VDS=4V

10-24

0

1

2

3

4

5

6

VGS (V)

Triantis et al

- is
questionable!gDSis not constant

- Te: in both parts of the channel
- thermal noise source in vel. sat. region: questionable!DrD is an ac resistance
- Old measurements (Abidi, ‘86) used
- SID ~ indep. of VDS (< 1.5x)

W=30mm; L=0.7mm

D.P. Triantis, A.N. Birbas and D. Kondis, Thermal noise modeling for short-channnel MOSFET’s, IEEE Trans. Electron Devices, Vol. 43, no. 11, pp.1950-1955, Nov. 1996.

Note: Region II noise increases with VGS; device is less saturated

Note: Calculations > measurements

10-21

Total noise - Triantis

Park & Park

Measurement

Region II noise

Park & Park

10-22

Region I noise

Triantis

Drain Current Noise (Amp2/Hz)

Region I noise

Park & Park

10-23

VDS=4V

Region II noise

Triantis

10-24

5

1

2

4

3

VGS (V)

Park and Park

- Mobility degradation due to channel field absent
- Carrier temperature, Te, used to model hot carrier effects
- Noise of VS region: intrinsic diffusion noise
- SiD=g2DS×(SvI+SvII) - questionable!
- Measurements (Abidi, ‘86)
- Temp:
- d~5-20 for EC=2-4V/mm

C.H. Park and Y.J. Park, Modeling of thermal noise in short-channel MOSFETs at saturation, Solid-State Electronics, Vol. 44, pp. 2053-2057, 2000.

G

(I)

D

S

(II)

DL

Lsat,VDSat

Leff,VDS

Knoblinger et al

- Te: in both parts of channel
- Te:
- meff=v(x)/E(x) in both parts of the channel: wrong!

G. Knoblinger, P. Klein & H. Tiebout, A new model for thermal channel noise of deep-submicron MOSFETs and its application in RF-CMOS design, IEEE J. Solid-State Cir., vol. 36, pp. 831-7, May 2001.

d~1.0 and noise from region Ia (T=lattice temperature) gave better fit to data at VGS>1.5V

Scholten et al

- CLM not taken into account

Te is not needed!

A.J. Scholten et al, Accurate thermal noise model for deep-submicron CMOS, IEDM Tech. Digest, pp. 155-158, 1999.

Chen & Deen

- Channel length modulation (CLM) is accounted for
- d=0 in experiments
- no Te needed

- No noise from VS region

C.H. Chen and M.J. Deen, Channel noise modeling of deep submicron MOSFETs, IEEE Trans. Electron Devices, vol. 49, pp. 1484-1487, Aug. 2002.

Scholten et al

- Modified Klaassen-Prins
- Takes into account CLM
- No noise from VS region
- A closed-form solution as a function of surface potential - too complicated! Difficult to provide insight to designers
- Not accurate for short channels at high VGS

A.J. Scholten et al, Noise modeling for RF CMOS circuit simulation, IEEE Trans. Electron Devices, Vol. 50, pp. 618- 632, Mar. 2003.

Han et al.

- Considers the channel field effect on mobility
- Starts from impedance field theory
- Uses Einstein equation in MOSFET channel : questionable! MOSFET channel is degenerate in strong inversion
- The result is based on thermal noise theory

K. Han, H.Shin and K. Lee, Analytical Drain Thermal Noise Current Model Valid for Deep Submicron MOSFETs, IEEE Trans. Electron Devices, vol. 51, pp. 261-269, Feb. 2004.

Dashed line is without this term

K. Han, H.Shin and K. Lee, Analytical Drain Thermal Noise Current Model Valid for Deep Submicron MOSFETs, IEEE Trans. Electron Devices, vol. 51, pp. 261-269, Feb. 2004.

G

D

S

(I)

(II)

Lelec

DL

Leff,VDS

Analytical Model

- Based on simple analytical drain current expression
- Includes the channel field effect
- Purely analytical (no integration, etc.)
- Suitable for circuit design

model

Analytical model

Analytical model

B. Wang, J.R. Hellums and C.G. Sodini, MOSFET thermal noise modeling for analog integrated circuits, IEEE JSSC vol. 29, pp. 833-835, July 1994.

- Noise and scaling
- For very short channel devices

CGS

Did(xo)

- Induced gate noise at x in channel
where

- Induced gate noise Dig(xo) is fully correlated with the channel thermal noise Did (xo)
- VDS becomes VDSsat in the saturation mode

- MOSFET channel- RC network at high f
- Gate capacitance and channel R

- Channel noise coupled to the gate→ SIG, correlation noise
- Frequency dependent
- Negligible as the channel length shrinks

8×10-23

L=0.97 mm

1×10-22

L=0.64 mm

L=0.97 mm

6×10-23

L=0.42 mm

1×10-23

L=0.27 mm

L=0.64 mm

Correlation Noise(A2/Hz)

4×10-23

SiG (A2/Hz)

L=0.18 mm

L=0.42 mm

1×10-24

2×10-23

L=0.27 mm

L=0.18 mm

0

1×10-25

2

4

5

6

1

3

1

10

Frequency (GHz)

Frequency (GHz)

M.J. Deen, C.H. Chen and Y. Cheng, MOSFET Modeling for Low Noise, RF Circuit Design, Proceedings of IEEE CICC, pp. 201-208, May 2002

NFmin

gm,max

- Channel length of devices reduced
- Increased gm and peak value of gm occurs at lower VGS values

- The faster increase in gm results in
- Reduced NFmin and the lowest NFmin is shifted to lower VGS values

gm

- Higher VDS bias will increase gm at the higher VGS region
- Higher gm will decrease NFmin at higher VGS region
- Decreased NFmin at higher VGS makes lowest NFmin less sensitive to VGS

NFmin

- MOSFET channel noise analytical models discussed
- Long channel case
- Short channel case

- Some ideas on how to use noise to design circuits
- Future applications demand low power
- MOSFET in moderate or weak inversion
- Noise models needed in these regions

- Professor C.H. Chen (McMaster University)
- Dr. Y. Cheng (Conexant/Skyworks)
- Funding - Rockwell/Conexant/Skyworks, USA and Gennum, Canada
- Funding - NSERC of Canada
- Funding - Micronet
- Funding - Canada Research Chair Program