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Chip level EMC measurements and simulations “Impact of Communications Technology to EMC“, COST 286 Workshop Vladimir Čeperić Hrvoje Marković PowerPoint PPT Presentation


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Chip level EMC measurements and simulations “Impact of Communications Technology to EMC“, COST 286 Workshop Vladimir Čeperić Hrvoje Marković Adrijan Bari ć Faculty of Electrical Engineering and Computing, University of Zagreb. Chip level EMC measurements and simulations.

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Chip level EMC measurements and simulations “Impact of Communications Technology to EMC“, COST 286 Workshop Vladimir Čeperić Hrvoje Marković

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  • Chip level EMC measurements and simulations

  • “Impact of Communications Technology to EMC“,

  • COST 286 Workshop

  • Vladimir Čeperić

  • Hrvoje Marković

  • Adrijan Barić

  • Faculty of Electrical Engineering and Computing,

  • University of Zagreb


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Chip level EMC measurements and simulations

  • European research program ROBUSPIC (ROBUst mixed signal design methodologies for Smart Power ICs).

  • UZAG’s focus points:

    • Development of parasitic extraction procedures suitable for EMC (electro-magnetic compatibility) analysis

    • Identification and modelling of EME (electro-magnetic emission) sources and analysis of EMI (electro-magnetic immunity)

    • Methodology for full-chip smart-power EMC simulation


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Outline

• Integrating EMC simulations in design flow

•Extraction and influence of PWR/GND parasitics

•EMC measurements system (IEC 62132-4 and IEC 61967-4)

•EMC test chip

•EMC optimizations

•Conclusion


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System level architecture design

& component spec.

Electrical circuit design

Physical pattern layout

Measurement & verification

PWR/GND lines/core of the circuit

separation

RC extraction of the core (Assura, ...)

RC (RLC) extraction ofPWR/GND lines

Spice netlist

EMC simulations

MOR

Design flow

RC/RLC parasitic extraction & EMC simulations


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The influence of the PWR/GND parasitics on the the emission levels

Comparison of invertor module and invertor module with HFSS extracted PWR/GND structure


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Influence of the package

SOIC8 package

NEED TO CONSIDER PACKAGING PARASITICS!


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Cadence Interface in Skill language

For conducted EME (IEC 61967-4)

- automatic generation of the Spectre netlist(s) with implementation of the 1 Ohm method

- transient simulations in Spectre

- manipulation of the results to determine the spectrum

- display of the results and automatic determination of the emission levels

For EM immunity (IEC 62132-4)

- Spectre analyses for defined

input power range

- determination of the inputpower

which causes malfunction

- display of the results


Iec 62132 4 for the measurement of em immunity with direct rf power injection method htvd lin l.jpg

IEC 62132-4 for the measurement of EM immunity with direct RF power injection method - HTVD LIN

RC load of the BUS, R=1 kOhm (to VBAT) and C=1 nF to GND

Operating at 20.0 kbit/sec, VBAT = 13.7 V,

Input frequency f=1 MHz


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EMC measurement system

  • EME and EMI HTVD LIN interface measurement system


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HTVD – LIN interface EMC measurements

EME measurements-

Voltage over 1 Ohm

(IEC 61947-4)

  • Matlab measuring automatization:

  • EME_EMI_measure_GPIB.m script

EMI measurements - DPI method (IEC 62132-4)

BUS

RxD

TxD


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HTVD – LIN interface 1 Ohm method

simulation

measurement


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EMC test chip

Chip for EMC testing:

high voltage and low voltage parts - ams C35/H35

digital

conducted EME testing structure (to evaluate the influence of backannotation)

LIN interface (conducted EME and EMI)

analog

LC oscillator (conducted EME, package parasitics model evaluation)


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EMC test chip

Chip for EMC testing:

two different packages used to

evaluate package influence on EME

and EMI

CLCC84

(Ceramic Leadless Chip Carrier)

JLCC84

(J-Leaded Ceramic Chip Carrier)


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EMC test chip

Chip for EMC testing:

conducted EME testing structure

LIN1, LIN2

LC oscillator1, LC oscillator2


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1.

Independent switching of 96 blocks

2.

Input of each block can either be common input signal or output of previous block

3.

Different widths of PWR/GND rails

4.

Different number of PWR/GND refreshes

5.

Output buffers with different output currents can be enabled

Conducted EME testing structure

Conducted EME teststructure enables:


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QUAD LC oscillator and VCO

  • High voltage (AMS H35 CMOS technology)

  • Cross-coupling increases significantly the precision of the oscillation frequency

  • Bond wires provide a resonant tank with high Q

  • conducted EME simulation and measurement

  • Bond wires used as inductance

    • package parasitics model evaluation

VCO


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LIN interface

  • LIN interface is design in high voltage technology (50V)

  • Design is tested for EM emission and EM immunity

    LIN interface from LIN2.0 standard ( Figure 3.1 )


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LIN interface EME optimization

  • Matlab script: EmissionLeveloptimization.m

After optimization: C-12-m

Before optimization: C-10-o

Optimization parameters: voltage levels on BUS, emission level of LIN interface,

width, length and number of fingers of the high voltage transistor at TxD input


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LIN interface EMS optimization

  • Matlab script: ImmunityOptimization.m

    • Psin source connected to BUS pin via 4.7nF capacitor

      • f1=150kHz, f2=1MHz, dBm=20

Without optimization:

max: td1=6.0755e-06, td2=5.691e-06

duty cycle min=0.4098

duty cycle max=0.4254

With optimization:

max: td1=5.2535e-06, td2=5.691e-06

duty cycle min=0.4278

duty cycle max= 0.42793

Optimization parameters: duty cycle and time delay (LIN 2.0 standard),

width, of the 10 transistors in Schmitt trigger


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Conclusion

  • EMC simulations can be incorporated into design flow

  • Package and PCB parasitics have to be considered

  • EMC measurement system according to IEC 62132-4 and IEC 61967-4 standards is being built

  • EMC test chip enables easy validation of EMC simulations vs. measurements

    • package model validation

    • comparison of 3D EM simulations vs. RC extraction simulations

  • Circuit optimizations wrt. EMC behavior are performed


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