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POLITECNICO DI BARI. Front-end for Silicon Photomultiplier (SiPM). SiPM : Silicon photomultiplier. MATRICE DI FOTODIODI A VALANGA POLARIZZATI IN GEIGER MODE. MOLTIPLICAZIONE DEI PORTATORI TRAMITE IL PROCESSO A VALANGA.

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POLITECNICO DI BARI

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Politecnico di bari

POLITECNICO DI BARI

Front-end for Silicon Photomultiplier (SiPM)


Politecnico di bari

SiPM: Silicon photomultiplier

MATRICE DI FOTODIODI A VALANGA POLARIZZATI IN GEIGER MODE

MOLTIPLICAZIONE DEI PORTATORI TRAMITE IL PROCESSO A VALANGA

AMPIEZZA DELl’IMPULSO DI USCITA PROPORZIONALE AL NUMERO DI FOTONI ASSORBITI

24x24 pixels

Politecnico di Bari


Politecnico di bari

Electrical model of a SiPM

  • Rq: quenching resistor

  • (hundreds of kW)

  • Cd: photodiode capacitance

  • (few tens of fF)

  • Cq: parasitic capacitance in parallel to Rq (smaller than Cd)

  • IAV: current source modelling the total charge delivered by a microcell during the avalanche

 Cg : parasitic capacitance due to the routing of the bias voltage to the N microcells, realized with a metal grid.

Example: metal-substrate unit area capacitance 0.03 fF/mm2

metal grid = 35% of the total detector area = 1mm2

 Avalanche time constants much faster than those introduced by the circuit:

IAV can be approximated as a short pulse containing the total amount of charge delivered by the firing microcell Q=DV(Cd+Cq), with DV=VBIAS-VBR

Cg  10pF, without considering the fringe parasitics

Politecnico di Bari


Politecnico di bari

Experimental validation of the model

Two different amplifiers have been used to read-out the FBK-irst SiPM

a) Transimpedance amplifier

BW=80MHz Rs=110W Gain=2.7kW

b) Voltage amplifier

BW=360MHz Rs=50W Gain=140

  • The model extracted according to the procedure described above has been used in the SPICE simulations

  • The fitting between simulations and measurements is quite good

Politecnico di Bari


Politecnico di bari

Front-end electronics: different approaches

Vbias

Vbias

Vbias

CF

SiPM

SiPM

SiPM

-

+

kIS=IOUT

IS

RS

RS

-

+

VOUT

VOUT

The charge Q delivered by the detector is collected on CF

If the maximum DVOUT is 3V and Q is 50pC (about 300 SiPM microcells), CF must be 16.7pF

Perspective limitations in dynamic range, die area, power consumption

Charge sensitive amplifier

Voltage amplifier

Current amplifier

A I-V conversion is realized by means of RS

The value of RS affects the gain

and the signal waveform

VOUT must be integrated to extract the charge information: thus a further V-I conversion is needed

RS is the (small) input impedance of the current buffer

The output current can be easily replicated (by means of current mirrors) and further processed (e.g. integrated)

The circuit is inherently fast

Less problems of dynamic range

Politecnico di Bari


Politecnico di bari

The CMOS current buffer

  • 0.35mm standard CMOS technology

  • Common gate configuration (M1)

  • Feedback applied to increase bandwidth and decrease input resistance (M3, M2)

  • SiPM bias (and gain) fine tuning possible by varying Vrif

Main simulated specs

  • Small signal bandwidth: 250MHz Input resistance: 17W

  • Total current consumption: 800uA Linearity dynamic range: about 50pC

  • Rise time of the output waveform: 400ps 3.3V power supply

  • Vrif variable in the range 1V÷2V

Politecnico di Bari


Politecnico di bari

Current

Buffer

Voltage

Amplifier

BNC

50Ω

Pulse Generator

BlueLed

SiPM

Iout

RIV

Experimental setup: blue LED light source

The circuit has been coupled to a SiPM realized by FBK-Irst

7V

Picture of the setup

Single dark pulse measurement (Vbr=-30.5V; Vbias=-32.5V)

Politecnico di Bari


Politecnico di bari

Dark pulse measurements

Charge measurements at Vbias = -32.5V

  • Comparison with a very fast discrete voltage amplifier front-end, used as a reference:

  • Average dark pulse charge

  • Integrated current buffer: 143fC

  • Discrete voltage amplifier: 142fC

  • The standard deviation is worse:

  • sint2sdisc

Blue LED measurements

  • Comparison with the ref. amplifier :

  • Average no. of fired microcells

  • Current buffer: 39

  • Ref. amplifier: 38.4

  • Standard deviation

  • Current buffer: 7.5

  • Ref. Amplifier: 7.2

Average number of fired microcells as a function of the input pulse width

Charge distribution for a 8.25ns input pulse width (in terms of no. of fired microcells)

Politecnico di Bari


Politecnico di bari

Architecture of the analog channel

  • Variable gain integrator: Gain: 1V/pC  0.33V/pC (2 bits);

    f = 200ns;

    Output voltage range: 0.3V ÷ 2.7V;

    Current mirror scaling factor 10:1

  • Current discriminator: Current mirror scaling factor 1:1;

    Threshold variable from 0 to 40µA (about 50 microcells @ VBIAS=-31.5V);

  • Baseline holder : Baseline value Vbl = 300mV

    Very slow time constant;

    Non-linearities added to prevent baseline shifts at increasing event rates

Politecnico di Bari


Politecnico di bari

Experimental setup: LED light source

  • SiPM A51 ( FBK – IRST )

  • Blue Led HSMB-C150

Voltage Buffer

50Ω Lemo

Ch_out

Ch_in

Chip

Disc

BlueLed

Pulse Generator

SiPM

Logic Buffer

Lemo

Vbias

Typical output waveforms

(Vbias=31.5V)

Politecnico di Bari


Politecnico di bari

Charge measurements (blue LED light source)

Ouput voltage vs pulse width for different gain settings

From the previous characterization measurements we have:

For pulse width = 9ns, n=115 fired microcells

If Vbias = 31.5 V, the total injected charge is QT= Q µcell(31.5V)*n = 6.9pC

If Vbias = 32.5 V, the total injected charge is QT= Q µcell(32.5V)*n = 17.3pC

Measurement are in good agreement with the expected results

Politecnico di Bari


Politecnico di bari

Design of the 8 channel ASIC: the Peak Detector (PD)

  • It is based on a P-MOS current mirror as a rectifying element

  • IBIAS added to improve the speed of operation, especially for small signals

VDD

M1

M2

Integrator output

_

OTA

+

out

VDISC

reset

IBIAS

MR

Chold=2pF

Politecnico di Bari


Politecnico di bari

Design of the 8 channel ASIC: the fast-OR

Vdd

trig_0

M0

Ibias

Vdd

Vdd

trig_1

I0

M1

Vbias

Ibias

Vbias

Cur_disc

MNBUF

MPBUF

F_or

Cbus

Ithresh

Vdd

trig_7

I2

I1

Ibias

M7

Ithresh= I2-(I0-I1)

  • Fast-OR circuit operating in current mode, to improve the speed of operation

  • Current buffer to reduce the input impedence

  • Current discriminator with fixed treshold

Politecnico di Bari


Politecnico di bari

Architecture of the test chip

a_out_0

PD

CSA

Curbuf

trig_0

Curdisc

Ext.

bias

ch_0

gain

Vrif

I_th

ADC_ck

PD

a_out_1

CSA

Curbuf

trig_1

reset_pad

Curdisc

data

ADC

MUX

Ext.

bias

ch_1

ck_pad

Read_out

logic

EOC

rw_pad

gain

Vrif

I_th

data_pad

I_th

Vrif

DAC

Vrif

DAC

I_th

a_out_7

PD

CSA

Curbuf

gain

Curdisc

MUX_sel

config_reg

Ext.

bias

ch_7

MUX_reg

srq_pad

gain

Vrif

I_th

Trig.

reg.

F_or

trig_7

Politecnico di Bari


Politecnico di bari

Design of the 8 channel ASIC: Layout

Politecnico di Bari


Politecnico di bari

Read-out procedure for the test chip

DATA_0

DATA

CLOCK

CLOCK

CHIP

SRQ

SRQ

FPGA

Package SMD

A)An event activates the SRQ bus (by default at Hi-Z)

B)FPGA gives a time-stamp to the event and takes control of the SRQ bus during the read-out procedure

C)SRQ, in its active state, is used to “freeze” the content of the trigger registers (no more trigger are accepted)

D)FPGA waits the time needed by the PDs to reach the peak and sends the CLOCK signal to the ASICs

F)The read-out logic starts the A/D conversions and sends the results to FPGA on the DATA_i pad

G)When all the conversions have been completed, FPGA releases the SRQ bus and sends a RESET signal

RESET

RESET

Politecnico di Bari


Politecnico di bari

Jitter measurements on fast-OR signal

Misure di jitter in presenza di un solo canale soprasoglia

Misure di jitter in presenza di due canali soprasoglia

Politecnico di Bari


Politecnico di bari

Design of the 32 channel ASIC: Logic Readout

pd_out_0

Vrif

I_th

gain

ex_ADC

DAC

Vrif

DAC

I_th

pd_out_1

ADC_2

MUX

data

DEMUX

config_reg

MUX

ADC_1

pd_out_31

reset_pad

DEMUX_reg

MUX_reg

rw_pad

MUX_reg

Logic Readout

EOC

ADC/Clock Manager

cK_ADC

coincidence_pad

ck_pad

trig_0

Trig.

reg.

SDI_pad

trig_1

F_or

srq_pad

SDO_pad

trig_31

SS

SPI interface

Politecnico di Bari


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