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# Multioperand Addition - PowerPoint PPT Presentation

Lecture 6. Multioperand Addition. Required Reading. Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design. Chapter 8, Multioperand Addition. Applications of multioperand addition. Inner product. Multiplication. n-1. n-1. p=a·x. s =  x (i) y (i) = . p (i). i=0.

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Behrooz Parhami,

Computer Arithmetic: Algorithms and Hardware Design

Chapter 8, Multioperand Addition

Inner product

Multiplication

n-1

n-1

p=a·x

s =  x(i) y(i)= 

p(i)

i=0

i=0

# of bits of S = log2 (Smax + 1)

=

= log2 (n (2k-1) + 1)  log2 n 2k =

= k + log2 n

Number of bits of the result

n-1

S =  x(i)

x(i) [0..2k-1]

i=0

Smin = 0

Smax = n (2k-1)

a2

b2

a1

b1

a0

b0

an-1

bn-1

c0

c3

c2

c1

cn

cn-1

. . .

FA

FA

FA

FA

s2

s1

s0

sn-1

cn-1

c2

c1

c0

bn-1

b2

b1

b0

an-1

a2

a1

a0

. . .

FA

FA

FA

FA

c3

c2

s2

s3

c1

s1

s0

sn-1

cn

cn-1

Example

20

22

23

24

21

x

y

z

0 1 0 1 0

1 1 0 1 1

1 0 1 1 1

s

c

0 0 1 1 0

1 1 011

x+y+z = s + c

in dot notation

in dot notation

x3 x2 x1 x0

y3 y2 y1 y0

z3 z2 z1 z0

w3 w2 w1 w0

s3 s2 s1 s0

c4 c3 c2 c1

w3 w2 w1 w0

c4 s3 s2 s1 s0

c4 c3 c2 c1

S5 S4 S3 S2 S1 S0

Carry-save adder for four operands

s0

s3

s2

c2

s1

c1

c3

c4

s0

s3

s2

s1

c4

c3

c2

c1

z

y

w

x

4

4

4

4

CSA

c

s

CSA

s’

c’

CPA

S

Carry-save adder for six operands

Implementation of

one-bit slice

CSA tree

seven numbers to two

six-bit numbers

in dot notation

k-bit numbers:

block diagram

Number of Inputs and Tree Height

Latency

LatencyCSA = h(n)  TFA + LatencyCPA(k, n)

Tree height

for n operands

Widths

typically

close to k bits

k .. k + log2 n

CSA

 k + log2 n

CPA

3

3

2

2

2

Parameters of tree carry-save adders (2)

Maximum number of inputs that can be reduced

to two by an h-level tree, n(h)

n(0) = 2

n(h) = n(h-1)

n(1) = 3

n(2) = 4

n(3) = 6

n(4) = 9

n(5) = 13

n(6) = 19

2 ( )h-1 < n(h)  2 ()h

Smallest height of the tree carry save adder

for n operands, h(n)

h(n) = 1 + h( )

2

n

3

h(2) = 0

h(n)  log ( )

n

3

2

2

Wallace trees

• Reduce the size of the final Carry Propagate Adder (CPA)

• Optimum from the point of view of speed

• Reduce the cost of the carry save tree

• Optimum (among the CSA trees) from the point of

• view of area

• Wallace reduces number of operands at earliest opportunity

• Goal of this is to have smallest number of bits for CPA adder

• However, sometimes having a few bits longer CPA adder does not affect the propagation delay significantly (i.e. carry-lookahead)

• Dadda seeks to reduce the number of FA and HA units

• May be at the cost of a slightly larger final CPA

22

23

21

20

24

a

b

c

d

e

0 1 0 1 0

1 1 0 1 1

1 0 1 1 1

1 0 1 1 1

1 1 1 1 1

s0

s1

s2

0 1 1 1 0

0 1 1 0 0

1 0 0 1 1

a+b+c+d+e = s0+s1+s2

using single CLB slice of a Virtex FPGA

d

e

a

b

w

w

w

w

w

PC

s1

s2

s0

CSA

CPA

w

y=a+b+c+d+e mod 2w

Carry Save Adder vs. 5-to-3 Parallel Counter

a

b

c

d

e

w

w

w

w

w

CSA

CSA

CSA

CPA

w

y=a+b+c+d+e mod 2w

Fig. 8.17 Dot notation for a (5, 5; 4)-counter and the use of such counters for reducing five numbers to two numbers.

Unequal columns

Generalized Parallel Counters

Multicolumn reduction

(5, 5; 4)-counter

Generalized parallel counter =

Parallel compressor

(2, 3; 3)-counter

Drop of such counters for reducing five numbers to two numbers.

Invert

(a) m = 2k

(b) m = 2k – 1

(c) m = 2k + 1

8.6 Modular Multioperand Adders

Fig. 8.20 Modular carry-save addition with special moduli.