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Timers. Lecture L4.4. Reference. TIM_16B8C Block User Guide. S12TIM16B8CV1.pdf. Timers. The 9S12C32 Programmable Timer Output Compares Pulse Train Using Interrupts Input Capture Measuring the Period of a Pulse Train Using Interrupts. PIM_9DP256 Block Diagram. Timer module.

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Timers

Timers

Lecture L4.4


Reference

Reference

TIM_16B8C

Block User Guide

S12TIM16B8CV1.pdf


Timers1

Timers

  • The 9S12C32 Programmable Timer

  • Output Compares

  • Pulse Train Using Interrupts

  • Input Capture

  • Measuring the Period of a Pulse Train Using Interrupts


Timers

PIM_9DP256

Block Diagram

Timer module


Timer counter

Timer Counter

Timer Count Register (TCNT)


Timer system control register 1

Timer System Control Register 1


Setting the timer count time

Setting the timer count time

Timer System Control Register 2 (TSCR2)


Timers

Main Timer Interrupt Flag 2 (TFLG2)


Timers

Timer Input Capture/Output Compare Select (TIOS)


Timers2

Timers

  • The 9S12DP256 Programmable Timer

  • Output Compares

  • Pulse Train Using Interrupts

  • Input Capture

  • Measuring the Period of a Pulse Train Using Interrupts


Timers

Timer Input Capture/Output Compare Registers 0-7

Main Timer Interrupt Flag 1 (TFLG1)


Timers

;Delay using Output Compares

TIOSEQU$0040 ; Timer Inp Cap.\Out Comp. Sel

TCNTEQU$0044 ; Timer Counter Register

TSCR1EQU$0046 ; Timer System Control Reg 1

TSCR2EQU$004D ; Timer System Control Reg 2

TFLG1EQU$004E ; Timer Interrupt Flag Reg 1

TC6EQU$005C ; Timer Output Compare Reg 6

OUTAEQU$FF4F

ORG$4000

main

jsrtimer_init

ldb#10

mn1tba

jsrhexasc

jsrouta

bsrsecond_delay

decb

bnemn1

swi


Timers

timer_init

ldaa#$40

staatios;select output compare 6

ldaa#$02

staatscr2;div by 4: 2 MHz timer clock

ldaa#$80

staatscr1;enable timer

lddtcnt

stdtc6;tc6 = current count

rts


Timers

ms25_delay;25 msec delay

pshd;save D

lddtc6

addd#50000;add 50000 to prev count

stdtc6

ldaa#$40

staatflg1;clear outpt comp 6 flag

msd1ldaatflg1

anda#$40;wait for timeout

beqmsd1

puld;restore D

rts

second_delay;delay 1 second

pshb;save B

ldab#40;40x25ms = 1000ms

sd1bsrms25_delay;delay 25 ms

decb; 40 times

bnesd1

pulb

rts


Pulse train example

Pulse Train Example


Timers

;Pulse train using output compares 7 and 6

TIOSequ $0040 ; Timer Input Cap.;Output Comp. Select

OC7Mequ $0042 ; Output Compare 7 Mask Register

OC7Dequ $0043 ; Output Compare 7 Data Register

TCNTequ $0044 ; Timer Counter Register

TSCR1equ $0046 ; Timer System Control Register 1

TCTL1equ $0048 ; Timer Control Register 1

TSCR2equ $004D ; Timer System Control Register 2

TFLG1equ $004E ; Timer Interrupt Flag Register 1

TC6equ $005C ; Timer Output Compare Register 6

TC7equ $005E ; Timer Output Compare Register 7

ORG$800

p_widthdw6625

perioddw17500


Timers

tinit

ldaa#$c0

staaTIOS ; select output compares 6 & 7

ldaa#$02

staaTSCR2 ; div by 4: 2 MHz timer clock

ldaa#$80

staaTSCR1 ; enable timer

ldaa TCNT

staaTC6

staaTC7 ; init cnt in TC6 & TC7

ldaa#$40

staaOC7M ; pulse train out PT6

clrOC7D ; PT6 goes low on TC7 match

ldaa#$30

staaTCTL1 ; set PT6 high on TC6 match

rts


Timers

ORG$4000

pulse

bsrtinit;initialize timer

pl1ldaa#$c0

staatflg1;clear output flags 6 and 7

lddtc7

adddperiod

stdtc7;TC7new = TC7old + PERIOD

adddp_width

stdtc6;TC6 = TC7new + P_WIDTH

pl2ldaatflg1;wait for PT6 to go low on

anda#$40; TC7 match and then high on

beqpl2; TC6 match

brapl1


Timers3

Timers

  • The 9S12DP256 Programmable Timer

  • Output Compares

  • Pulse Train Using Interrupts

  • Input Capture

  • Measuring the Period of a Pulse Train Using Interrupts


Pulse train

Pulse Train


Timers

;Pulse train using output compares 7 and 6

TIOSequ $0040 ; Timer Input Cap.;Output Comp. Select

OC7Mequ $0042 ; Output Compare 7 Mask Register

OC7Dequ $0043 ; Output Compare 7 Data Register

TCNTequ $0044 ; Timer Counter Register

TSCR1equ $0046 ; Timer System Control Register 1

TCTL1equ $0048 ; Timer Control Register 1

TIE equ $004C ; Timer Interrupt Enable Register 1

TSCR2equ $004D ; Timer System Control Register 2

TFLG1equ $004E ; Timer Interrupt Flag Register 1

TC6equ $005C ; Timer Output Compare Register 6

TC7equ $005E ; Timer Output Compare Register 7

TC6_IVEC equ$0FE4 ; Timer Channel 6 interrupt vector

ORG$800

p_widthdw6625

perioddw17500

ORG$4000

pulsei

bsrtinit;initialize timer

pl1brapl1


Timers

tinit

sei; disable interrupts

ldaa#$c0

staaTIOS ; select output compares 6 & 7

ldaa#$02

staaTSCR2 ; div by 4: 2 MHz timer clock

ldaa#$80

staaTSCR1 ; enable timer

ldaa TCNT

staaTC6

staaTC7 ; init cnt in TC6 & TC7

ldaa#$40

staaOC7M ; pulse train out PT6

clrOC7D ; PT6 goes low on TC7 match

ldaa#$30

staaTCTL1 ; set PT6 high on TC6 match

ldd#tc6_intser

stdTC6_IVEC; save int vector

ldaa#$40

staaTIE; enable TC6 interrupts

cli; enable interrupts

rts


Timers

tc6_intser

lddtc7

adddperiod

stdtc7;TC7new = TC7old + PERIOD

adddp_width

stdtc6;TC6 = TC7new + P_WIDTH

ldaa#$c0

staatflg1;clear output flags 6 and 7

rti


Timers4

Timers

  • The 9S12DP256 Programmable Timer

  • Output Compares

  • Pulse Train Using Interrupts

  • Input Capture

  • Measuring the Period of a Pulse Train Using Interrupts


Input capture

Input Capture


Timers

pwidth.asm

; Use input capture to measure width of single pulse.

; Polling mode -- no interrupts

; Use TC2 -- signal on PT2

TIOSequ $0040 ; Timer Input Cap.;Output Comp. Select

TCNTequ $0044 ; Timer Counter Register

TSCR1equ $0046 ; Timer System Control Register 1

TCTL4equ $004B ; Timer Control Register 4

TIE equ $004C ; Timer Interrupt Enable Register 1

TSCR2equ $004D ; Timer System Control Register 2

TFLG1equ $004E ; Timer Interrupt Flag Register 1

TC2equ $0054 ; Timer Input Capture Register 6

org$800

pwidthdw0


Timers

pwidth.asm (cont.)

org$4000

main

bsrtic_init;initialize timer

bsrpulse_width;measure single pulse width

swi

tic_init

clrtios; select all input captures

clrtscr2; div by 1: 8 MHz timer clock

ldaa#$80

staatscr1; enable timer

rts


Timers

pwidth.asm (cont.)

pulse_width

ldaa#$10

staatctl4;capture on rising edge

ldaa#$04

staatflg1;clear C2F flag

pw1ldaatflg1

anda#$40;wait for rising edge

beqpw1

lddtc2;read t1

std2,-sp;save t1

ldaa#$04

staatflg1;clear C2F flag

ldaa#$20

staatctl4;capture on falling edge

pw2ldaatflg1

anda#$40;wait for falling edge

beqpw2

lddtc2;read t2

ldaa#$04

staatflg1;clear C2F flag

subd2,sp+;d = t2 - t1

stdpwidth;save pwidth

rts


Timers5

Timers

  • The 9S12DP256 Programmable Timer

  • Output Compares

  • Pulse Train Using Interrupts

  • Input Capture

  • Measuring the Period of a Pulse Train Using Interrupts


Timers

; Measuring the period of a pulse train.

; Use interrupts

; Use TC1 -- signal on PT1

TIOSequ $0040 ; Timer Input Cap.;Output Comp. Select

TCNTequ $0044 ; Timer Counter Register

TSCR1equ $0046 ; Timer System Control Register 1

TCTL4equ $004B ; Timer Control Register 4

TIE equ $004C ; Timer Interrupt Enable Register 1

TSCR2equ $004D ; Timer System Control Register 2

TFLG1equ $004E ; Timer Interrupt Flag Register 1

TFLG2equ $004F ; Timer Interrupt Flag Register 2

TC1equ $0054 ; Timer Input Capture Register 1

TC1_IVEC equ$0FEE ; Timer Channel 1 interrupt vector

TOF_IVEC equ$0FE0 ; Timer overflow flag interrupt vector

Out1byt equ$FF52 ; display hex value of byte at X

org$800

ovcntdw0

ovcnt_olddw0

tic1_olddw0

dperiodrmb4


Timers

init_ic

sei

clrtios; select input capture 1

clrtscr2; div by 1: 8 MHz timer clock

ldaa#$80

staatscr1; enable timer

ldaa#$40

staatctl4; rising edge of TC1

ldaa#$02

staatflg1; clear any old flags

ldaa#$80

staatflg2

staatscr2; enable TOI interrupt

ldaa#$20

staatie; enable TC1 interrupt

ldd#tc1_intser

stdTC1_IVEC; save int vector

ldd#tof_intser

stdTOF_IVEC; save int vector

cli

rts


Timers

tof_intser

lddovcnt

addd#1

stdovcnt;inc ovcnt

ldaa#$80

staatflg2;clear TOF

rti

ovcnt

TC1

ovcnt_old

tic1_old


Timers

tc1_intser

lddtc1;get new inp capture

std2,-sp;push it

lddovcnt;get new ovcnt

std2,-sp;push it

lddtic1_old;get old inp capture

std2,-sp;push it

lddovcnt_old;get old ovcnt

std2,-sp;push it

ldd6,sp;get new inp capture

stdtic1_old;store it in tic1_old

ldd4,sp;get new ovcnt

stdovcnt_old;store it in ovcnt_old

tsx;x = sp

bsrdminus;x -> ddiff

ldd0,x

stddperiod;store dperiod

ldd2,x

stddperiod+2

ldaa#$02

staatflg1;clear C1F flag

rti


Timers

Subtracting Double Numbers

ovcnt

tc1

ovcnt_old

tic1_old


Timers

org$4000

main

bsrinit_ic;initialize timer

mn0ldx#dperiod

ldab#4

mn1jsrout1byt;output dperiod decb; to screen

bnemn1

ldy#30

jsrms_delay

bramn0; continuously


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