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Studies of Timing Structural Properties for Early Evaluation of Circuit Design

Studies of Timing Structural Properties for Early Evaluation of Circuit Design. Andrew B. Kahng*, Ryan Kastner, Stefanus Mantik, Majid Sarrafzadeh and Xiaojian Yang UCLA CS Dept., Los Angeles, CA, USA *UCSD CSE and ECE Depts., La Jolla, CA, USA. Abstract.

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Studies of Timing Structural Properties for Early Evaluation of Circuit Design

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  1. Studies of Timing Structural Properties for Early Evaluation of Circuit Design Andrew B. Kahng*, Ryan Kastner, Stefanus Mantik, Majid Sarrafzadeh and Xiaojian Yang UCLA CS Dept., Los Angeles, CA, USA *UCSD CSE and ECE Depts., La Jolla, CA, USA

  2. Abstract The Rent parameter has been widely used to characterize interconnect complexity of designs. The Rent power-law relationship is often used for a priori wire estimation, which is an enabling component of timing closure methodologies. However, the Rent parameter does not explicitly address timing information. In this work, we propose studies of circuit timing structure that can potentially help identify useful characterizations of the timing behavior of the design. We believe that such characterizations can allow us early identification of designs for which timing closure will prove difficult. One characterization of the timing structure is analogous to the Rent parameter: we propose a temporal Rent characterization based on the analysis of the number of active signals intersecting a specified timing boundary within the clock period.

  3. Timing Structural Properties • Motivation: • Early “a priori” timing prediction à la Rent’s Rule • A step towards timing closure through identification of critical temporal areas of a design • Innovations: • Active Interval of a timing edge • Timing Structure Analysis for crosstalk, peak power and other timing properties • Temporal Analysis of Special Topologies

  4. Pin Vertex Net Edge Gate Edge Preliminaries: Timing Parameters • Pin Graph A A D D B C B C Pin Graph Combinatorial Circuit • Traditional Timing Parameters • RAT: AAT: • New Timing Parameter: Active Interval • Edge eijis active at time t iff startij t  endij, where

  5. Active Interval Distribution Graph • x-axis: size of the active interval; y-axis: the number of edges with active interval less than or equal to x • A large initial slope corresponds to a large number of nets with small active intervals • small active duration for nets  less chance for crosstalk

  6. Clock Cycle Activity Graph • x-axis: clock cycle offset from zero; y-axis: the number of edges that are currently active at time x • A “flatter” plot corresponds to a more well-distributed signal activity • long tail  critical paths

  7. Temporal Analogue to Rent’s Rule Extend Rent’s Rule to Temporal Domain

  8. Special-Case Circuit Analysis Ring Binary-tree Mesh Clique

  9. Rentian Circuits For single-source Rentian circuit: For a symmetrical Rentian circuit with two latches at opposite ends of the netlist { T(t): number of active edges at time t A rentian circuit example: A=3, p=0.5

  10. Conclusions • Pessimist model of active interval (worst case, overestimate) • Studies of circuit timing structure that help identify useful characterizations of the timing behavior of the design • size of active intervals: possibility of having crosstalk problems • nets activity: distribution of slacks among timing paths • On going works • translate the analyses into estimators for optimization • identify additional timing behaviors

  11. Studies of Timing Structural Properties for Early Evaluation of Circuit Design Andrew B. Kahng*, Ryan Kastner, Stefanus Mantik, Majid Sarrafzadeh and Xiaojian Yang UCLA CS Dept., Los Angeles, CA, USA *UCSD CSE and ECE Depts., La Jolla, CA, USA

  12. Motivation • Rent’s Rule • T = ABp (T = ave # external nets, B = ave # of cells) • used for a priori estimation of wirelength and congestion • lack of timing information • Temporal Rent’s Rule • add timing domain to traditional Rent’s rule • used for a priori estimation of timing related behavior, e.g., crosstalks, slacks, cycle time, etc. • need to find (power) laws

  13. Pin Vertex Net Edge Gate Edge Preliminaries: Timing Parameters • Pin Graph A A D D B C B C Pin Graph Combinatorial Circuit • Traditional Timing Parameters • RAT: AAT: • New Timing Parameter: Active Interval • Edge eijis active at time t iff startij t  endij, where

  14. Signal Activity Behavior Plots • small active duration for nets  less chance for crosstalk • well distributed intervals  good slack budgeting

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