On the Improvement of Statistical Timing Analysis

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On the Improvement of Statistical Timing Analysis. Rajesh Garg Nikhil Jayakumar Sunil P. Khatri Department of Electrical &amp; Computer Engineering, Texas A&amp;M University, College Station. Outline. Motivation Previous Work Our Approach Phase 1 Phase 2 Propagating Arrival Times Experiments

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### On the Improvement of Statistical Timing Analysis

Rajesh Garg

Nikhil Jayakumar

Sunil P. Khatri

Department of Electrical & Computer Engineering,

Texas A&M University, College Station.

Outline
• Motivation
• Previous Work
• Our Approach
• Phase 1
• Phase 2
• Propagating Arrival Times
• Experiments
• Results
• Conclusions & Future Work
Motivation
• Increasing process variation has necessitated statistical analysis of timing.
• Alternative to performing static timing analysis over several process corners.
• Useful way to get better yield estimates.
• Current approaches to statistical timing are not readily being accepted by chip designers.
• Time consuming
• Pessimistic
SSTA-Statistical Static Timing Analysis
• Based on the principles of Static Timing Analysis (STA).
• STA propagates arrival times using SUM, MAX operations.
• SSTA: implement SUM and MAX operations for delay distributions.
• Identify only structurally long paths.
• Such paths may not be sensitizable!
SSTA- Sources of Pessimism
• Spatial Correlations
• Path Correlations
• Approximation of PDFs by Gaussian distributions.
• Approximation when calculating MAX of two distributions.
• False paths.
• Assumption that gate delay can be represented by a single Normal distribution.
Our Contributions
• Eliminate False paths
• Use a sensitizable timing analysis tool.
• Delay for each input transition of a gate is represented by a Normal distribution.
• Use the particular Normal distribution corresponding to input transition of a gate that results in large sensitizable delays.
• In SSTA, the delay of a gate is represented by a single Normal distribution.
Previous Work
• “False-path-aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation”, J.-J.Liou et.al (DAC 2002)
• Then, attempt to find sensitizable paths.
• Assume delay of a gate is represented by a single Gaussian
• Ignores difference in input arrival times.
• Our Approach:
• First find sensitizable input vector transitions, then perform statistical timing analysis.
• Allows us to consider the actual input transitions occurring at the inputs of each gate.
• Takes input arrival time differences into consideration.
Our Approach
• Phase 1
• Find set of sensitizable critical delay transitions. This yields a more accurate analysis
• Phase 2
• Perform Statistical Timing Analysis on the vector transitions from Phase 1.
• Exploit information on input transition at each gate (from Phase 1) to get a yet more accurate analysis.
• Use the sensepackage in SIS to find the maximum sensitizable delay.
• Sense uses a SAT solver to verify if a particular delay is sensitizable.
• Starts with longest structural delay (from static timing analysis).
• Keeps reducing delay in fixed steps until a sensitizable maximum delay D is found
• Implicitly eliminates false paths.
• Modified the sense package to return all the primary input vector transitions that cause the largest delays.
• Returns primary input vectors that cause these large delays.
• Our modification also generates all possible previous values on the primary inputs that cause the output to transition.
• Insert complement of largest sensitizable vector in the SAT instance for sense and run sense again iteratively
• Repeat until a user-specified number of delay-critical transitions is collected.
Phase 2: Compute Output Delay Distributions
• Perform Monte-Carlo analysis on set of delay-critical vector transitions.
• Propagate arrival times using information on the transition occurring (from Phase 1).
• Utilize delay distribution for the actual input transition observed at each gate.
Propagating Arrival Times
• For regular Static Timing Analysis (for falling output)
• Delay = MAX{ (ATa + MAX(D00→11, D01→11)) , (ATb + MAX(D00→11, D10→11)) }

= 35+55.3 = 90.3

0

10

35

90.3

a

a

55.3ps

c

b

b

55.3ps

c

a

b

c

Propagating Arrival Times
• More accurate estimate for falling output (used in our approach)
• Delay = MAX{ (ATa + D00→11), (ATb + D10→11) }

= 35 + 42.7 = 77.7

0

10

35

77.7

90.3

a

55.3ps

c

b

42.7ps

a

b

c

Propagating Arrival Times
• For regular Static Timing Analysis (for rising output)
• Delay = MAX{ (ATa + MAX(D11→00, D11→01)) , (ATb + MAX(D11→00, D11→10)) }

= 35+53.0 = 88.0

0

10

35

88.0

50.5ps

a

c

b

53.0ps

a

b

c

Propagating Arrival Times
• More accurate estimate for rising output (used in our approach)
• Delay = MIN{ (ATa + D11→01), (ATb + D11→00) }

0

10

35

60.5

88.0

= 10 + 50.5 = 60.5

50.5ps

a

c

b

30.5ps

Propagating Arrival Times
• Plot of output delay with different input arrival times.
• STA and our new approach are compared with SPICE
• One input transitioning at a fixed time.
• Swept transition time of other input

NAND2: 00→11

NAND2: 11→00

Propagating Arrival Times
• Similarly for a 3-input NAND3 gate with inputs {a,b,c} and output {O}.
• For falling output transition – all inputs need to switch to logic 1.
• 000→100→110→111
• ATout = MAX{ (ATa + D000 →111), (ATb + D100 →111), (ATc + D110 →111) }
• For rising output transition – only one of the inputs needs to switch to logic 0.
• 111→011→001→000
• ATout = MIN{ (ATa + D111 →011), (ATb + D111 →001), (ATc + D111 →000) }
Experiments
• Standard-cell library of 8 cells
• INV1X, INV2X, NAND2, NAND3, NAND4, NOR2, NOR3, NOR4.
• Used SPICE to characterize the cells.
• Used 0.1um BPTM process.

Variations applied

• Created table of values for mean and standard deviation of the delay for all possible transitions for a set of loads.
Delay Distribution example
• Delay of a gate cannot be represented by a single Gaussian distribution.
• Depends on input transitions.

NAND2: Falling output transition

NAND2: Rising output transition

Experiments
• Phase 1
• Compute top 50 delay-critical vector transitions.
• Phase 2
• Use knowledge of input transitions at each gate from Phase 1.
• Propagate arrival times (using method discussed).
• Propagate 1000 times
• For each transition, choose a random value of delay from a Gaussian distribution.
• Use values of m and s from a pre-characterized table for the particular vector transition appearing at the gate.
• Use same m + ns delay point for all input transitions of gate
Experiments
• Compared our approach (StatSense) with Monte-Carlo based SSTA (10000 MC iterations).
• Compared results for a set of ISCAS and MCNC benchmark circuits.
• Also compared results from 50 critical vector transitions versus 25 critical vector transitions.
• 1000 MC runs for each vector transition.
Results
• Our approach (StatSense) is significantly less pessimistic.
• Takes ~2.3X more time to run (50000 MC runs compared to 10000)
Results
• StatSense with 25 vector transitions takes only 50% more time than SSTA.
• Runtime is not 5X (for 50 vector transitions) or 2.5X (for 25 transitions)
• If there is no transition at output of a gate, delay computations in the fanout of a gate can be avoided.
• No such pruning possible in SSTA.
Example – apex7
• Delay histogram is significantly less pessimistic.
• Circuit delay is not a Gaussian distribution.
Conclusions and Future Work
• Current statistical timing analysis approaches are pessimistic.
• Pessimism due to false paths and
• Assumption that delay of a gate can be represented by a single Gaussian distribution.
• Our approach is significantly less pessimistic.
• Future work
• Decrease runtimes.
• Explore methods to find the minimum number of vector transitions required to get a realistic statistical timing result.
• Use the sense package in SIS to find the maximum sensitizable delay.
• Sense uses a SAT solver to verify if a particular delay is sensitizeable.
• Starts with longest structural delay (from a static timing analysis).
• Keeps reducing delay in steps till a delay D is sensitizable.
• Implicitly eliminates false paths.
• Modified sense package to return all the primary input vector transitions that causes this maximum delay.
• Returns current primary input vector that causes this maximum delay.
• Also, generate all possible previous values of the primary input vector that cause the output to transition.
• Insert complement of largest sensitizable vector in sense’s SAT instance and run sense again.
• Repeat till a large-enough (user-specified) set of delay-critical transitions is collected.
Propagating Arrival Times
• Naïve estimate
• Delay = MAX(ATa, ATb) + D00→11= 35+55.3 = 90.3

0

10

35

90.3

a

a

55.3ps

c

b

b

55.3ps

c