Directions in LowPower CAD. Dennis Sylvester University of Michigan [email protected] http://vlsida.eecs.umich.edu With acknowledgements to: Prof. David Blaauw, Dr. Sarvesh Kulkarni, Saumil Shah, Kavi Chopra. Topics. A new dualVth assignment formulation DualVdd power distribution
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Directions in LowPower CAD
Dennis Sylvester
University of Michigan
http://vlsida.eecs.umich.edu
With acknowledgements to: Prof. David Blaauw, Dr. Sarvesh Kulkarni, Saumil Shah, Kavi Chopra
S. Narendra et al [ICCAD ’03]
Switching
Subthreshold
leakage
HVt
LVt
Mixed Gate
HVt Gate
LVt Gate
FF
VDDH
VDDL
FF
VDDL Swing
DC Current
IN
FF
Need for Level Conversion
FF
FF
OUT
IN
Noncritical
Critical
CVS
ECVS
Coupled
issues
Circuits
Level shifting
Algorithms
VDD assignment
Physical design
VDD Granularity
Power delivery
Distribution
Generation
Finegrained
Islanding
Power supply current demanded by a dualVDD circuit is significantly lower than the corresponding singleVDD circuit, allowing robust power delivery within available resources (decap, C4, wiring)
VDD
ECVS
LpkgH
RpkgH
Lskt
Rskt
Lmb2
Rmb2
Lmb1
Rmb1
2
+
RhfH
Rpkg_capH
RdieH
RblkH
VDDH
Load
VDDH
I(VDDH)
LhfH
Lpkg_capH
LblkH
CdieH

ChfH
Cpkg_capH
CblkH
1

RhfL
RblkL
RdieL
Rpkg_capL
VDDL
Load
VDDL
I(VDDL)
LhfL
LblkL
Lpkg_capL
CdieL
+
ChfL
CblkL
Cpkg_capL
3
LpkgL
RpkgL
Lmb1
Rmb1
Lskt
Rskt
Lmb2
Rmb2
Intel, “Intel Pentium 4 processor in the 432 pin/Intel 850 Chipset Platform,” 2002.
SingleVDD
DualVDD
VDDH
VDDL
GND
VDDH + VDDL row
VDDH + VDDL row
VDDH + VDDL row
VDDH + VDDL row
DualVDD segregated
DualVDD segregated
VDDH + VDDL row
VDDH + VDDL row
VDDH + VDDL row
DualVDD finegrained
Segregated placement constrains placer leading to higher core area and wirelength
C. Yeh, et al., “Layout techniques supporting the use of dual supply voltages for cellbased designs,” Proc. DAC, 1999.
M. Igarashi, et al., “A lowpower design method using multiple supply voltages,” Proc. ISLPED, 1997.
DualVDD standard cells topologies
SingleVDD
DualVDD SharedGND
DualVDD DualGND
3rail cell
4rail cell
VDDH
VDDL
GND
(shared)
VDDL
GNDL
VDDH
GNDH
VDD
GND
VDDL
GNDL
VDDH
VDDL
VDDH
GNDH
GND
(shared)
Obtain current
consumption of
Single/Dual VDD
designs (SPICE)
Regional
Global
Obtain Dual
VDD design
Original Single
VDD design
Local
Single
VDD
Lib file
Dual
VDD
Lib file
Break down die
into “local” &
“regional” areas
Placement
database
(Cadence)
Measure voltage
droop/bounce
Size each wire
segment in each
local area using
effective ,β &simulate grid
Calculate local,regional, global& effective &
for each wiresegment
VDDH
VDDL
GND
Measure wire
congestion
VDDL = 0.6V
VDDL = 0.8V
DualVDD grid no less robust than singleVDD grid
P
P
Vth
Delay
Leff
Power
Chip Performancespace
Process Parameterspace
Optical Proximity Effects Variation
Chemical Mechanical Polishing Variations
Low Leakage
PoorTiming
Timing Yield Loss
Good Timing
High Leakage
Power Yield Loss
This Work: Optimize the timing and power yield using gate sizing
Yield: A utility function defined w.r.t the JPDF of leakage and timing
Tconst
Pconst
Timing Analysis [Sapatnekar03, Chandu05](d, d)
d
Delay
Correlation (1 parameter)
Power Analysis (l, l)
Delay and Power Bivariate JPDF (d, d, l, l, )
l
Log(Leakage)
Cut Edge Time(CT)
Size Up 7
Traditional Incremental Timing
Required Arrival Time (RT)
Arrival Time (AT)
Unperturbed Sub Graph
2
6
9
Unperturbed
Left Sub Graph
Unperturbed
Right Sub Graph
8
3
10
1
4
7
5
MaxCut Edge Time (CT)
Chopra, et al., ICCAD05
BB
controller
Critical
Noncritical
Critical
DELAY
POWER
Correlated
ONE BIAS FOR ALL GATES
Important to cluster gates to leverage ABB effectively
Generate sample scenarios
Solve BB assignmentfor each scenario
Scenario ‘2’
Scenario ‘1’
Leff_4.2
Leff_4.1
ρi,j
Gate
BBPDF
4
4
7
7
3
3
Leff_5.1
Leff_5.2
Leff_7.2
Leff_7.1
Leff_3.1
Leff_3.2
5
5
Leff_2.2
Leff_2.1
Scenario ‘x’
Leff_4.x
DETERMINISTICALLY optimize each scenario (i.e., tune each gate for each die scenario)
Leff_1.2
Leff_1.1
Leff_6.1
Leff_6.2
2
2
4
7
6
6
1
1
3
Leff_5.x
Leff_7.x
Leff_3.x
5
Leff_2.x
Leff_1.x
Leff_6.x
2
6
1
Clustering
Postsilicon tuning
Generate PDFs of optimal actions