Stt ram project
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STT-RAM Project. Initial Estimates and Results of Cell Sizing. Expected MTJ Parameters (Ilya/Pedram). I-STT R P ≈ 500-700 Ω TMR ≈ 100-120% Lowest write energy: V WRITE ≈ 0.6-1V t PULSE ≈ 1-5ns C-STT R P ≈ 600-800 Ω TMR ≈ 30-50% Lowest write energy: V WRITE ≈ 1.2-2.0V

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STT-RAM Project

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Stt ram project

STT-RAM Project

Initial Estimates and

Results of Cell Sizing


Expected mtj parameters ilya pedram

Expected MTJ Parameters (Ilya/Pedram)

  • I-STT

    • RP ≈ 500-700Ω

    • TMR ≈ 100-120%

    • Lowest write energy:

      • VWRITE ≈ 0.6-1V

      • tPULSE ≈ 1-5ns

  • C-STT

    • RP ≈ 600-800Ω

    • TMR ≈ 30-50%

    • Lowest write energy:

      • VWRITE ≈ 1.2-2.0V

      • tPULSE ≈ 0.2-0.5ns


Reference sram cell

Reference SRAM Cell

  • For IBM65: F = 0.1μm

  • SRAM Size: 0.625μm2 = 62.5F2

~1.087μm

~0.575μm


Stt ram cell sizing

STT-RAM Cell Sizing

  • For a 2 finger device, cell area is approx:0.61μm x (WFINGER + 0.2μm)

    • 50F2 → 620nm/50nm x2

    • 35F2 → 380nm/50nm x2

    • 25F2 → 220nm/50nm x2

27.5 F2

52.5 F2

(OLD CELLS)


I stt results for balanced voltage

I-STT Results for “Balanced” Voltage

  • VWL = 1.0V

    • VDD = 1V; RP ≈ 500-700Ω; TMR ≈ 100-120%

  • VWL = 1.2V (15-40% increase in IWRITE/VWRITE)

    • VDD = 1V; RP ≈ 500-700Ω; TMR ≈ 100-120%


I stt results for balanced current

I-STT Results for “Balanced” Current

  • VWL = 1.0V

    • VDD = 1V; RP ≈ 500-700Ω; TMR ≈ 100-120%

  • VWL = 1.2V (15-40% increase in IWRITE/VWRITE)

    • VDD = 1V; RP ≈ 500-700Ω; TMR ≈ 100-120%


C stt results for balanced voltage

C-STT Results for “Balanced” Voltage

  • VWL = 1.0V

    • VDD = 1V; RP ≈ 600-800Ω; TMR ≈ 30-50%

  • VWL = 1.2V (15-40% increase in IWRITE/VWRITE)

    • VDD = 1V; RP ≈ 600-800Ω; TMR ≈ 30-50%


C stt results for balanced current

C-STT Results for “Balanced” Current

  • VWL = 1.0V

    • VDD = 1V; RP ≈ 600-800Ω; TMR ≈ 30-50%

  • VWL = 1.2V (15-40% increase in IWRITE/VWRITE)

    • VDD = 1V; RP ≈ 600-800Ω; TMR ≈ 30-50%


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