Image rotation
Download
1 / 10

Image Rotation - PowerPoint PPT Presentation


  • 75 Views
  • Uploaded on

Image Rotation. Daniel E. Michek. Image Rotation Details Raster Scan Output. Choice to rotate input image or output image Hotelling transform w/ basis vectors cos(t) and sin(t) Rotate input image (raster scan order data output) Sx = Dx*cos(t) + Dy*sin(t), Sy = Dy*cos(t) - Dx*sin(t)

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Image Rotation' - nash


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Image rotation

Image Rotation

Daniel E. Michek

Xilinx Confidential


Image rotation details raster scan output
Image Rotation DetailsRaster Scan Output

  • Choice to rotate input image or output image

  • Hotelling transform w/ basis vectors cos(t) and sin(t)

    • Rotate input image (raster scan order data output)

      • Sx = Dx*cos(t) + Dy*sin(t), Sy = Dy*cos(t) - Dx*sin(t)

    • Rotate output image (random order data output)

      • Dx = Sx*cos(t) - Sy*sin(t), Dy = Sy*cos(t) + Sx*sin(t)

Xilinx Confidential


Issues with random ordered data output
Issues with random ordered data output

  • The incoming image is sent pixel by pixel to the random memory destination address.

  • This causes holes in the output if not over sampled.

  • Corners are not cleared because not all memory locations are written to with each image.

Xilinx Confidential


Demo algorithm brief
Demo Algorithm Brief

  • Resources -128x128 single channel 8bit

    • 881 Slices, 1 BRAM, 12 MULT18X18

    • Uses 4x pixel speed access to memories for bilinear method with 1 frame latency

  • Arbitrary input from files

    • Automatically accommodates arbitrary file size and pixel bit precision with PreLoadFcn and StopFcn calls

  • Pan and Zoom incorporated

  • Simulation time for 128x128 image is ~8 minutes

Xilinx Confidential


Demo algorithm details
Demo Algorithm Details

  • Requires 1 read memory and 1 write memory (2x image memory total)

  • Offset must be added to center the image

    • This gives an excellent opportunity to pan the image and zoom in. (Demo center and pan control)

  • Invalid addresses and data must be blocked

  • Bilinear precision allows up to 214 interpolation accuracy (27 width*27 height) with only 4 MULT18X18s

Xilinx Confidential


Center and zoom
Center and Zoom

  • Non-centered Image

  • Zoomed Image (0.25)

Xilinx Confidential


Customer specific adaptations
Customer Specific Adaptations

  • Multi-Channel

    • Can take advantage of extra space in memory data width

    • 3 channel 12bit data fits in same memory footprint when using x33 memories

  • Faster memory access

    • Increases total memory to 8x but allow for 4 parallel reads (4x speed)

    • 8bit data can sit in same memory footprint when using x32 memories

Xilinx Confidential


Qualitative comparison

64x64 MatLab imrotate

64x64 ximrotate

Qualitative Comparison

Xilinx Confidential


Microblaze multimedia board support package
MicroBlaze MultiMedia Board Support Package

  • ZBT Memories mapped

  • ADV7185 (video input decoder) in process

    • Component/Svideo

    • Will output only valid image data

    • Awaiting customer specific requirements to match tokens with their proprietary board (Titan-Visicom)

  • ADV7194 (video output encoder) in process

    • Component/Svideo/VGA

    • RGB not planned

Xilinx Confidential


Mbmm board support package continued
MBMM Board Support Package (continued)

  • 1 Supertoken contains bitstream allowing for use of any component, sub-tokens allow for hardware specific builds

    • Allows for seamless flow from System Generator/Partial HWIL to full HWIL to free running board

  • Download on web/~danielm

    • Self installing setup from m-file corrects for your install location

Xilinx Confidential


ad