Idempotent processor architecture
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Idempotent Processor Architecture. Marc de Kruijf Karthikeyan Sankaralingam Vertical Research Group UW-Madison. MICRO 2011, Porto Alegre. Idempotent Processor Architecture. idempotent regions. “live state”. idempotence : re-execution has no side-effects (inputs are preserved). =.

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Idempotent Processor Architecture

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Idempotent processor architecture

Idempotent Processor Architecture

Marc de Kruijf

KarthikeyanSankaralingam

Vertical Research Group

UW-Madison

MICRO 2011, Porto Alegre


Idempotent processor architecture1

Idempotent Processor Architecture

idempotent regions

“live state”

idempotence:

re-execution has no side-effects (inputs are preserved)

=

region entry point:

implicit checkpoint in the live state of the program

applications naturally decompose into idempotent regions

2


Idempotent processor architecture2

Idempotent Processor Architecture

idempotent recovery

CHECKPOINT

conventional

recovery

idempotent

recovery

recovery without checkpoints – just re-execute

3


Idempotent processor architecture3

Idempotent Processor Architecture

idempotent processors

RF

conventional

processor

Decode

Exec

WB

Fetch

Issue

RF

idempotent

processor

Exec

WB

Exec

WB

Decode

Decode

Fetch

Decode

Exec

WB

Issue

Issue

Issue

simpler decode, issue, execute, and writeback

4


Presentation overview

Presentation Overview

❶ Idempotent Recovery

❷ Idempotent Processors

❸ Evaluation

5


Idempotent recovery

Idempotent Recovery

example

1. R2 = add R0, R1

2. R3 = ld [R2 + 4]

3. R2 = add R2, R4

4. beqz R2, NEXT

idempotent

region

“Something went wrong executing instruction 2!”

(page fault, corrupted write, etc.)

“No problem – just re-execute from instruction 1!”

6


Idempotent recovery1

Idempotent Recovery

idempotent regions

idempotent “regions”: freely re-executable program regions

=

sizes inhibited by clobberantidependences (WAR after no RAW)

normal compiler:

custom compiler:

adds some runtime overhead (typically 2-10%)

special marker instruction

7


Idempotent recovery2

Idempotent Recovery

average idempotent region sizes

frequent clobber antidependences – can be removed, but requires large restructuring effort

with funcparams marked

using C/C++ “restrict”

limited aliasing

information

ARM micro-ops

43

select benchmarks

benchmark suites (geo-mean)

(geo-mean)

8


Presentation overview1

Presentation Overview

❶ Idempotent Recovery

❷ Idempotent Processors

❸ Evaluation

9


Idempotent processors

Idempotent Processors

exploring the opportunity

Vdd

branch

In

Out

issue

execute

retire

exceptions &

out-of-order retirement

branch misprediction

hardware faults

in-order

out-of-order

multi-core

10


Idempotent processors1

Idempotent Processors

steps one, two, and three

Step 1: construct a high-performance in-order processor

ARM Cortex-A8 (‘05) IBM Cell SPE (‘05) Intel Atom (‘08)

Step 2: prune out unnecessary parts

↓ power, area, & complexity

Step 3: optimize for energy efficiency

↑ performance at low cost

11


Step 1 construction

Step 1: Construction

v1.0

Integer

Integer

Branch

Fetch

Decode & Issue

Multiply

RF

Add

Load/Store

Exception!

Ld

FP

12


Step 1 construction1

Step 1: Construction

v1.0

Integer

Bypass

Integer

Branch

Fetch

Decode,

Rename,

& Issue

Multiply

RF

Load/Store

Flush?

FP

Staged instruction completion

13


Step 1 construction2

Step 1: Construction

v1.0 v1.1

Integer

Bypass

Integer

Branch

Fetch

Decode,

Rename,

& Issue

Multiply

RF

Load/Store

Flush?

FP

FP exceptions handled in hardware.

Separate FP unit implements full IEEE 754.

IEEE FP

?

14


Step 1 construction3

Step 1: Construction

v1.0v1.1 v1.2

Load miss?

Have to flush!

Integer

Bypass

Integer

Branch

Fetch

Decode,

Rename,

& Issue

Multiply

RF

Load/Store

Flush?

Replay?

Flush?

FP

Replay queue

IEEE FP

15


Step 1 construction4

Step 1: Construction

v1.0v1.1v1.2 v1.3

Integer

Bypass

Integer

Branch

Too Complicated!

Fetch

Decode,

Rename,

& Issue

Multiply

RF

Load/Store

Flush?

Replay?

FP

Replay queue

IEEE FP

16


Step 2 simplification

Step 2: Simplification

idempotent edition (simple)

  • What is gone?

  • staging register file (6-entries)

  • replay queue (8-entries)

  • entire rename pipeline stage

  • IEEE-compliant floating point unit

  • pipeline flush for exceptions and replays

  • all associated control logic

Integer

Integer

Branch

Fetch

Decode & Issue

Multiply

RF

Load/Store

FP

17


Step 3 optimization

Step 3: Optimization

idempotent edition (fast)

Integer

SDB*

Integer

Branch

Fetch

Decode & Issue

Multiply

RF

Load/Store

FP

details in paper…

* Slice Data Buffer (SDB) – Continual Flow Pipelines. ASPLOS ‘04

18


Presentation overview2

Presentation Overview

❶ Idempotent Recovery

❷ Idempotent Processors

❸ Evaluation

19


Evaluation

Evaluation

idempotent processor performance

speed-up over in-order

select benchmarks

benchmark suites (geo-mean)

(geo-mean)

20


Evaluation1

Evaluation

summary

21


Presentation overview3

Presentation Overview

❶ Idempotent Recovery

❷ Idempotent Processors

❸ Evaluation

22


Future work

Future Work

– quantify power/complexity benefits

(build real hardware prototype)

– more general error conditions

(hardware faults, branch prediction, etc.)

– impact on multithreading/multiprocessors

(re-execution currently assumes no interference)

– region overlapping (“region pipelining”)

(analagous to overlapping checkpoints)

23


Conclusions

Conclusions

recovery using idempotence

– recovery without checkpoints

multiple uses and multiple designs

– uses: exception, speculation, fault recovery, and more

– designs: in-order, out-of-order, multi-core, GPU, and more

in this work: exception recovery + in-order design

– simplified out-of-order execution

– better performance at equal or lower power/complexity

24


Back up slides

Back-up Slides

25


Optimal idempotent region size

Optimal Idempotent Region Size?

(rough sketch – graph not to scale)

serialization overhead

compiler formation overhead (many factors)

re-execution overhead

overhead

region size

26


Optimal processor design

Optimal Processor Design?

~ 250mW

~ 2.5W

Compiler

overheads

dominate?

Re-execution

overheads

dominate?

Best potential?

Single-issue in-order

Dual-issue OoO

Dual-issue in-order

Quad-issue OoO

27


Out of order issue processors

Out-of-Order Issue Processors?

  • Some additional challenges….

    • Re-execution overhead high if mis-speculation frequent

      • cannot restart from point of mis-speculation, and hence…

      • re-execution overhead on average ≈ half the region

  • Example: branch misprediction

    • With in-order issue, simple to flush/drain pipeline

    • With out-of-order issue, we can use idempotence but…

      • 5 branches/region @ 90% confidence ≈ 41% re-execution rate

Speculate only high-confidence branches

Hybrid checkpointing/idempotence

…?

28


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