Performance optimization of single phase level sensitive circuits
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PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS. BARIS TASKIN AND IVAN S. KOURTEV. UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING. Outline. Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions.

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Performance optimization of single phase level sensitive circuits

PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS

BARIS TASKIN AND

IVAN S. KOURTEV

UNIVERSITY OF PITTSBURGH DEPARTMENTOF ELECTRICAL ENGINEERING


Outline
Outline

  • Introduction

  • Timing Constraints

  • LP Model Formulation

  • Experimental Results

  • Conclusions


Introduction
Introduction

  • Large-scale SOC

  • Time borrowing (cycle stealing)

  • Clock skew scheduling

  • Clock/Timing schedule

  • Minimum clock period


Background
Background

  • Local data path

  • Graph


Latch operation
Latch Operation

Positive level-sensitive


Time borrowing
Time Borrowing

Higher Operating Frequency!

Flip-Flop based

Latch based


Clock skew
Clock Skew

Tskew(i,f) = ti - tf

Clock signal delay at the initial register

Clock signal delay at the final register


Clock skew scheduling
Clock Skew Scheduling

Higher Operating Frequency!

Zero clock skew

Non-zero clock skew


Optimization problem
Optimization Problem

Time borrowing

+

Clock skew scheduling

  • Latch-based

  • Non-zero clock skew

  • Flip-flop-based

  • Zero clock skew



Outline1
Outline

  • Introduction

  • Timing Constraints

  • LP Model Formulation

  • Experimental Results

  • Conclusions


Constraints
Constraints

Constant

or

Variable?


Latching constraints

af

Af

Latching Constraints




Propagation constraints
Propagation Constraints

Min!

Max!


Outline2
Outline

  • Introduction

  • Timing Constraints

  • LP Model Formulation

  • Experimental Results

  • Conclusions



Modified big m mbm method
Modified big M (MBM) Method


Mbm method example

M

MBM Method Example

+1000c

C1a: ca

C1b: cb

b

c

c

a

NON-LINEAR

LINEAR


Lp model formulation
LP Model Formulation

[Synchronization Constraint-I]


Implementation and model highlights
Implementation and Model Highlights

  • C++ implementation

  • Off-shelf optimizer (CPLEX)

  • Provide stand-alone model

    • Robust, fast

    • Sensitivity analysis


Outline3
Outline

  • Introduction

  • Timing Constraints

  • LP Model Formulation

  • Experimental Results

  • Conclusions


Timing analysis
Timing Analysis

OUTPUT

INPUT



Additional constraints
Additional Constraints

Clock signal delays at R1 and R4

Clock Pin

Circuit

C

tR1 = tR4 = c

c:constant

R2

R5

R1

R3

...

R4



Outline4
Outline

  • Introduction

  • Timing Constraints

  • LP Model Formulation

  • Experimental Results

  • Conclusions


Conclusions
Conclusions

  • Increased performance

    • Time borrowing

    • Clock skew scheduling

  • Complete framework for timing

    analysis

    • Multi-phase synchronization


Performance optimization of single phase level sensitive circuits1

PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS

QUESTIONS

BARIS TASKIN AND

IVAN S. KOURTEV

UNIVERSITY OF PITTSBURGH DEPARTMENTOF ELECTRICAL ENGINEERING


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