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PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS. BARIS TASKIN AND IVAN S. KOURTEV. UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING. Outline. Introduction Timing Constraints LP Model Formulation Experimental Results Conclusions.

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performance optimization of single phase level sensitive circuits

PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS

BARIS TASKIN AND

IVAN S. KOURTEV

UNIVERSITY OF PITTSBURGH DEPARTMENTOF ELECTRICAL ENGINEERING

outline
Outline
  • Introduction
  • Timing Constraints
  • LP Model Formulation
  • Experimental Results
  • Conclusions
introduction
Introduction
  • Large-scale SOC
  • Time borrowing (cycle stealing)
  • Clock skew scheduling
  • Clock/Timing schedule
  • Minimum clock period
background
Background
  • Local data path
  • Graph
latch operation
Latch Operation

Positive level-sensitive

time borrowing
Time Borrowing

Higher Operating Frequency!

Flip-Flop based

Latch based

clock skew
Clock Skew

Tskew(i,f) = ti - tf

Clock signal delay at the initial register

Clock signal delay at the final register

clock skew scheduling
Clock Skew Scheduling

Higher Operating Frequency!

Zero clock skew

Non-zero clock skew

optimization problem
Optimization Problem

Time borrowing

+

Clock skew scheduling

  • Latch-based
  • Non-zero clock skew
  • Flip-flop-based
  • Zero clock skew
outline1
Outline
  • Introduction
  • Timing Constraints
  • LP Model Formulation
  • Experimental Results
  • Conclusions
constraints
Constraints

Constant

or

Variable?

outline2
Outline
  • Introduction
  • Timing Constraints
  • LP Model Formulation
  • Experimental Results
  • Conclusions
mbm method example

M

MBM Method Example

+1000c

C1a: ca

C1b: cb

b

c

c

a

NON-LINEAR

LINEAR

lp model formulation
LP Model Formulation

[Synchronization Constraint-I]

implementation and model highlights
Implementation and Model Highlights
  • C++ implementation
  • Off-shelf optimizer (CPLEX)
  • Provide stand-alone model
    • Robust, fast
    • Sensitivity analysis
outline3
Outline
  • Introduction
  • Timing Constraints
  • LP Model Formulation
  • Experimental Results
  • Conclusions
timing analysis
Timing Analysis

OUTPUT

INPUT

additional constraints
Additional Constraints

Clock signal delays at R1 and R4

Clock Pin

Circuit

C

tR1 = tR4 = c

c:constant

R2

R5

R1

R3

...

R4

outline4
Outline
  • Introduction
  • Timing Constraints
  • LP Model Formulation
  • Experimental Results
  • Conclusions
conclusions
Conclusions
  • Increased performance
    • Time borrowing
    • Clock skew scheduling
  • Complete framework for timing

analysis

    • Multi-phase synchronization
performance optimization of single phase level sensitive circuits1

PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS

QUESTIONS

BARIS TASKIN AND

IVAN S. KOURTEV

UNIVERSITY OF PITTSBURGH DEPARTMENTOF ELECTRICAL ENGINEERING

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