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VLSI Arithmetic Adders & Multipliers. Prof. Vojin G. Oklobdzija University of California http://www.ece.ucdavis.edu/acsel. Digital Computer Arithmetic belongs to Computer Architecture, however, it is also an aspect of logic design.

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Vlsi arithmetic adders multipliers

VLSI ArithmeticAdders & Multipliers

Prof. Vojin G. Oklobdzija

University of California

http://www.ece.ucdavis.edu/acsel


Introduction

Digital Computer Arithmetic belongs to Computer Architecture, however, it is also an aspect of logic design.

The objective of Computer Arithmetic is to develop appropriate algorithms that are utilizing available hardware in the most efficient way.

Ultimately, speed, power and chip area are the most often used measures, making a strong link between the algorithms and technology of implementation.

Introduction

Computer Arithmetic


Basic operations

Addition

Multiplication

Multiply-Add

Division

Evaluation of Functions

Multi-Media

Basic Operations

Computer Arithmetic


Addition of binary numbers

Addition of Binary Numbers


Addition of binary numbers1

Addition of Binary Numbers

Full Adder. The full adder is the fundamental building block of most arithmetic circuits:  

The sum and carry outputs are described as:

ai

bi

Full

Adder

Cout

Cin

si

Computer Arithmetic


Addition of binary numbers2

Inputs

Outputs

ci

ai

bi

si

ci+1

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Addition of Binary Numbers

Propagate

Generate

Propagate

Generate

Computer Arithmetic


Full adder implementation

Full-Adder Implementation

Full Adder operations is defined by equations:

Carry-Propagate:

and Carry-Generate gi

One-bit adder could be implemented as shown

Computer Arithmetic


High speed addition

High-Speed Addition

One-bit adder could be implemented more efficiently

because MUX is faster

Computer Arithmetic


The ripple carry adder

The Ripple-Carry Adder

Computer Arithmetic


The ripple carry adder1

The Ripple-Carry Adder

From Rabaey

Computer Arithmetic


Inversion property

Inversion Property

From Rabaey

Computer Arithmetic


Minimize critical path by reducing inverting stages

Minimize Critical Path by Reducing Inverting Stages

From Rabaey

Computer Arithmetic


Ripple carry adder

Ripple Carry Adder

Carry-Chain of an RCA implemented using multiplexer from the standard cell library:

Critical Path

Oklobdzija, ISCAS’88

Computer Arithmetic


Manchester carry chain realization of the carry path

Manchester Carry-Chain Realization of the Carry Path

  • Simple and very popular scheme for implementation of carry signal path

Computer Arithmetic


Original design

Original Design

T. Kilburn, D. B. G. Edwards, D. Aspinall, "Parallel Addition in Digital Computers:

A New Fast "Carry" Circuit", Proceedings of IEE, Vol. 106, pt. B, p. 464, September 1959.

Computer Arithmetic


Manchester carry chain cmos

Manchester Carry Chain (CMOS)

  • Implement P with pass-transistors

  • Implement G with pull-up, kill (delete) with pull-down

  • Use dynamic logic to reduce the complexity and speed up

Kilburn, et al, IEE Proc, 1959.

Computer Arithmetic


Pass transistor realization in dpl

Pass-Transistor Realization in DPL

Computer Arithmetic


Carry skip adder

Carry-Skip Adder

MacSorley, Proc IRE 1/61

Lehman, Burla, IRE Trans on Comp, 12/61

Computer Arithmetic


Carry skip adder1

Carry-Skip Adder

Bypass

From Rabaey

Computer Arithmetic


Carry skip adder n bits k bits group r n k groups

Carry-Skip Adder:N-bits, k-bits/group, r=N/k groups

Computer Arithmetic


Carry skip adder2

Carry-Skip Adder

k

Computer Arithmetic


Variable block adder oklobdzija barnes ibm 1985

Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Carry chain of a 32 bit variable block adder oklobdzija barnes ibm 1985

Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Carry chain of a 32 bit variable block adder oklobdzija barnes ibm 19851

Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

6

5

5

4

4

3

3

D=9

1

1

Any-point-to-any-point delay = 9 D

as compared to 12 D for CSKA

Computer Arithmetic


Carry chain block size determination for a 32 bit variable block adder oklobdzija barnes ibm 1985

Carry-chain block size determination for a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Delay calculation for variable block adder oklobdzija barnes ibm 1985

Delay Calculation for Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Delay model:

Computer Arithmetic


Variable block adder oklobdzija barnes ibm 19851

Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Variable Group Length

Oklobdzija, Barnes, Arith’85

Computer Arithmetic


Carry chain of a 32 bit variable block adder oklobdzija barnes ibm 19852

Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Variable Block Lengths

  • No closed form solution for delay

  • It is a dynamic programming problem

Computer Arithmetic


Delay comparison variable block adder oklobdzija barnes ibm 1985

Delay Comparison: Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Delay comparison variable block adder

Delay Comparison: Variable Block Adder

VBA

CLA

VBA- Multi-Level

Computer Arithmetic


Vlsi arithmetic lecture 4

VLSI ArithmeticLecture 4

Prof. Vojin G. Oklobdzija

University of California

http://www.ece.ucdavis.edu/acsel


Review

Review

Lecture 3


Variable block adder oklobdzija barnes ibm 19852

Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Carry chain of a 32 bit variable block adder oklobdzija barnes ibm 19853

Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Carry chain of a 32 bit variable block adder oklobdzija barnes ibm 19854

Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

6

5

5

4

4

3

3

D=9

1

1

Any-point-to-any-point delay = 9 D

as compared to 12 D for CSKA

Computer Arithmetic


Carry chain block size determination for a 32 bit variable block adder oklobdzija barnes ibm 19851

Carry-chain block size determination for a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Delay calculation for variable block adder oklobdzija barnes ibm 19851

Delay Calculation for Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Delay model:

Computer Arithmetic


Variable block adder oklobdzija barnes ibm 19853

Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Variable Group Length

Oklobdzija, Barnes, Arith’85

Computer Arithmetic


Carry chain of a 32 bit variable block adder oklobdzija barnes ibm 19855

Carry-chain of a 32-bit Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Variable Block Lengths

  • No closed form solution for delay

  • It is a dynamic programming problem

Computer Arithmetic


Delay comparison variable block adder oklobdzija barnes ibm 19851

Delay Comparison: Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Delay comparison variable block adder1

Delay Comparison: Variable Block Adder

Square Root Dependency

VBA

Log Dependency

CLA

VBA- Multi-Level

Computer Arithmetic


Circuit issues

Circuit Issues

  • Adder speed can not be estimated based on:

    • logic gates in the critical path

    • number of transistors in the path

    • logic levels in the path

  • Estimating Adders speed is much more complex and many of the “fast” schemes may be misleading you.

Computer Arithmetic


Fan out dependency

Fan-Out Dependency

Computer Arithmetic


Fan in dependency

Fan-In Dependency

This looks like

“Logical Effort”

(1985)

Computer Arithmetic


Delay comparison variable block adder oklobdzija barnes ibm 19852

Delay Comparison: Variable Block Adder(Oklobdzija, Barnes: IBM 1985)

Computer Arithmetic


Vlsi arithmetic adders multipliers

Computer Arithmetic


Carry lookahead adder weinberger and smith 1958

Carry-Lookahead Adder(Weinberger and Smith, 1958)

ARITH-13: Presenting Achievement Award to Arnold Weinberger of IBM (who invented CLA adder in 1958)

Ref: A. Weinberger and J. L. Smith, “A Logic for High-Speed Addition”, National Bureau of Standards, Circ. 591, p.3-12, 1958.

Computer Arithmetic


Cla definitions one bit adder

CLA Definitions: One-bit adder

Computer Arithmetic


Cla definitions 4 bit adder

CLA Definitions: 4-bit Adder

Computer Arithmetic


Carry lookahead adder 4 bits

Carry-Lookahead Adder: 4-bits

Gj

Pj

Computer Arithmetic


Carry lookahead adder

Carry-Lookahead Adder

One gate delay D

to calculate p, g

One D to calculate

P and two for G

Three gate delays

To calculate C4(j+1)

Compare that to 8 D in RCA !

Computer Arithmetic


Carry lookahead adder weinberger and smith

Carry-Lookahead Adder(Weinberger and Smith)

Additional two gate delays

C16 will take a total of 5D vs. 32D for RCA !

Computer Arithmetic


32 bit carry lookahead adder

32-bit Carry Lookahead Adder

Computer Arithmetic


Carry lookahead adder weinberger and smith original derivation 1958

Carry-Lookahead Adder(Weinberger and Smith: original derivation, 1958 )

Computer Arithmetic


Carry lookahead adder weinberger and smith original derivation

Carry-Lookahead Adder(Weinberger and Smith: original derivation )

Computer Arithmetic


Carry lookahead adder weinberger and smith please notice the similarity with parallel prefix adders

Carry-Lookahead Adder (Weinberger and Smith)please notice the similarity with Parallel-Prefix Adders !

Computer Arithmetic


Carry lookahead adder weinberger and smith please notice the similarity with parallel prefix adders1

Carry-Lookahead Adder (Weinberger and Smith)please notice the similarity with Parallel-Prefix Adders !

Computer Arithmetic


Motorola cla implementation example

Motorola: CLA Implementation Example

A. Naini, D. Bearden and W. Anderson, “A 4.5nS 96b CMOS Adder Design”,

Proceedings of the IEEE Custom Integrated Circuits Conference, May 3-6, 1992.


Critical path in motorola s 64 bit cla

Critical path in Motorola's 64-bit CLA

4.8nS

1.05nS

1.7nS

3.75nS

2.7nS

2.0nS

2.35nS

Computer Arithmetic


Motorola s 64 bit cla conventional pg block

Motorola's 64-bit CLAconventional PG Block

no better situation here !

carry ripples locally

5-transistors in the path

Basically, this is MCC performance with Carry-Skip.

One should not expect any better results than VBA.

Computer Arithmetic


Motorola s 64 bit cla modified pg block

Motorola's 64-bit CLAModified PG Block

Intermediate propagate signals Pi:0

are generated to speed-up C3

still critical path resembles MCC

Computer Arithmetic


Motorola s 64 bit cla

3.9nS

1.8nS

2.2nS

3.55nS

2.9nS

3.2nS

Motorola's 64-bit CLA

Computer Arithmetic


Vlsi arithmetic adders multipliers

3.9nS

4.8nS

1.8nS

1.05nS

2.2nS

1.7nS

3.55nS

3.75nS

2.9nS

3.2nS

2.7nS

2.0nS

2.35nS

Computer Arithmetic


Delay optimized cla

Delay Optimized CLA

B. Lee, V. G. Oklobdzija

Journal of VLSI Signal Processing, Vol.3, No.4, October 1991


Delay optimized cla lee oklobdzija 91

Delay Optimized CLA: Lee-Oklobdzija ‘91

(a.) Fixed groups and levels

(b.) variable-sized groups, fixed levels

(c.) variable-sized groups and fixed levels

(d.) variable-sized groups and levels

Computer Arithmetic


Two levels of logic implementation of the carry block

Two-Levels of Logic Implementation of the Carry Block

Computer Arithmetic


Two levels of logic implementation of the carry lookahead block

Two-Levels of Logic Implementation of the Carry-Lookahead Block

Computer Arithmetic


Three levels of logic implementation of the carry block restricted fan in

Three-Levels of Logic Implementation of the Carry Block (restricted fan-in)

Computer Arithmetic


Three levels of logic implementation of the carry lookahead restricted fan in

Three-Levels of Logic Implementation of the Carry Lookahead (restricted fan-in)

Computer Arithmetic


Delay optimized cla lee oklobdzija 911

Delay Optimized CLA: Lee-Oklobdzija ‘91

Delay: Three-level BCLA

Delay: Two-level BCLA

Computer Arithmetic


Delay optimized cla lee oklobdzija 912

Delay Optimized CLA: Lee-Oklobdzija ‘91

(a.) 2-level BCLA D=8.5nS (b.) 3-level BCLA D=8.9nS

Computer Arithmetic


Ling s adder

Ling’s Adder

Huey Ling, “High-Speed Binary Adder”

IBM Journal of Research and Development, Vol.5, No.3, 1981.

Used in: IBM 3033, IBM 168, Amdahl V6, HP etc.


Ling s derivations

ai

bi

ci+1

ci

si

Ling’s Derivations

define:

gi implies Ci+1 which implies Hi+1 , thus: gi= gi Hi+1

Computer Arithmetic


Ling s derivations1

Ling’s Derivations

From:

and

because:

fundamental expansion

Now we need to derive Sum equation

Computer Arithmetic


Ling adder

Ling Adder

Ling’s equations:

Variation of CLA:

Ling, IBM J. Res. Dev, 5/81

Computer Arithmetic


Ling adder1

Ling Adder

Ling’s equation:

Variation of CLA:

Ling uses different transfer function.

Four of those functions have desired

properties (Ling’s is one of them)

see: Doran, IEEE Trans on Comp. Vol 37, No.9 Sept. 1988.

Computer Arithmetic


Ling adder2

Ling Adder

Conventional:

Fan-in of 5

Ling:

Fan-in of 4

Computer Arithmetic


Advantages of ling s adder

Advantages of Ling’s Adder

  • Uniform loading in fan-in and fan-out

  • H16 contains 8 terms as compared to G16 that contains 15.

  • H16 can be implemented with one level of logic (in ECL), while G16 can not.

    (Ling’s adder takes full advantage of wired-OR, of special importance when ECL technology is used)

Computer Arithmetic


Vlsi arithmetic lecture 5

VLSI ArithmeticLecture 5

Prof. Vojin G. Oklobdzija

University of California

http://www.ece.ucdavis.edu/acsel


Review1

Review

Lecture 4


Ling s adder1

Ling’s Adder

Huey Ling, “High-Speed Binary Adder”

IBM Journal of Research and Development, Vol.5, No.3, 1981.

Used in: IBM 3033, IBM S370/168, Amdahl V6, HP etc.


Ling s derivations2

ai

bi

ci+1

ci

si

Ling’s Derivations

define:

gi implies Ci+1 which implies Hi+1 , thus: gi= gi Hi+1

Computer Arithmetic


Ling s derivations3

Ling’s Derivations

From:

and

because:

fundamental expansion

Now we need to derive Sum equation

Computer Arithmetic


Ling adder3

Ling Adder

Ling’s equations:

Variation of CLA:

Ling, IBM J. Res. Dev, 5/81

Computer Arithmetic


Ling adder4

ai-1

ai

bi-1

bi

ci+1

ci-1

ci

si-1

si

Hi+1

Hi

gi, ti

gi-1, ti-1

Ling Adder

Ling’s equation:

Variation of CLA:

Ling uses different transfer function.

Four of those functions have desired

properties (Ling’s is one of them)

see: Doran, IEEE Trans on Comp. Vol 37, No.9 Sept. 1988.

Computer Arithmetic


Ling adder5

Ling Adder

Conventional:

Fan-in of 5

Ling:

Fan-in of 4

Computer Arithmetic


Advantages of ling s adder1

Advantages of Ling’s Adder

  • Uniform loading in fan-in and fan-out

  • H16 contains 8 terms as compared to G16 that contains 15.

  • H16 can be implemented with one level of logic (in ECL), while G16 can not (with 8-way wire-OR).

    (Ling’s adder takes full advantage of wired-OR, of special importance when ECL technology is used - his IBM limitation was fan-in of 4 and wire-OR of 8)

Computer Arithmetic


Ling weinberger notes

Ling: Weinberger Notes

Computer Arithmetic


Ling weinberger notes1

Ling: Weinberger Notes

Computer Arithmetic


Ling weinberger notes2

Ling: Weinberger Notes

Computer Arithmetic


Advantage of ling s adder

Advantage of Ling’s Adder

  • 32-bit adder used in: IBM 3033, IBM S370/ Model168, Amdahl V6.

  • Implements 32-bit addition in 3 levels of logic

  • Implements 32-bit AGEN: B+Index+Disp in 4 levels of logic (rather than 6)

  • 5 levels of logic for 64-bit adder used in HP processor

Computer Arithmetic


Implementation of ling s adder in cmos s naffziger a subnanosecond 64 b adder isscc 96

Implementation of Ling’s Adder in CMOS(S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96)

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Vlsi arithmetic adders multipliers

S. Naffziger, ISSCC’96

Computer Arithmetic


Ling adder critical path

Ling Adder Critical Path

Computer Arithmetic


Ling adder circuits

Ling Adder: Circuits

Computer Arithmetic


Lcs4 critical g path

LCS4 – Critical G Path

Computer Arithmetic


Lcs4 logical effort delay

LCS4 – Logical Effort Delay

Computer Arithmetic


Results

Results:

  • 0.5u Technology

  • Speed: 0.930 nS

  • Nominal process, 80C, V=3.3V

See: S. Naffziger, “A Subnanosecond 64-b Adder”, ISSCC ‘ 96

Computer Arithmetic


Prefix adders and parallel prefix adders

Prefix Addersand Parallel Prefix Adders


Vlsi arithmetic adders multipliers

from: Ercegovac-Lang

Computer Arithmetic


Prefix adders

Prefix Adders

Following recurrence operation is defined:

(g, p)o(g’,p’)=(g+pg’, pp’)

such that:

(g0, p0)

i=0

Gi, Pi =

(gi, pi)o(Gi-1, Pi-1 )

1 ≤ i ≤ n

ci+1 = Gi

for i=0, 1, ….. n

(g-1, p-1)=(cin,cin)

c1 = g0+ p0 cin

This operation is associative, but not commutative

It can also span a range of bits (overlapping and adjacent)

Computer Arithmetic


Vlsi arithmetic adders multipliers

from: Ercegovac-Lang

Computer Arithmetic


Parallel prefix adders variety of possibilities

Parallel Prefix Adders: variety of possibilities

from: Ercegovac-Lang

Computer Arithmetic


Vlsi arithmetic adders multipliers

Pyramid Adder:M. Lehman, “A Comparative Study of Propagation Speed-up Circuits in Binary Arithmetic Units”, IFIP Congress, Munich, Germany, 1962.

Computer Arithmetic


Parallel prefix adders variety of possibilities1

Parallel Prefix Adders: variety of possibilities

from: Ercegovac-Lang

Computer Arithmetic


Parallel prefix adders variety of possibilities2

Parallel Prefix Adders: variety of possibilities

from: Ercegovac-Lang

Computer Arithmetic


Hybrid bk ks adder

Hybrid BK-KS Adder

Computer Arithmetic


Parallel prefix adders s knowles 1999

Parallel Prefix Adders: S. Knowles 1999

operation is associative: h>i≥j≥k

operation is idempotent: h>i≥j≥k

produces carry: cin=0

Computer Arithmetic


Parallel prefix adders ladner fisher

Parallel Prefix Adders: Ladner-Fisher

Exploits associativity, but not idempotency.

Produces minimal logical depth

Computer Arithmetic


Parallel prefix adders ladner fisher 16 8 4 2 1

Parallel Prefix Adders: Ladner-Fisher(16,8,4,2,1)

Two wires at each level. Uniform, fan-in of two.

Large fan-out (of 16; n/2); Large capacitive loading combined with the long wires (in the last stages)

Computer Arithmetic


Parallel prefix adders kogge stone

Parallel Prefix Adders: Kogge-Stone

Exploits idempotency to limit the fan-out to 1.

Dramatic increase in wires. The wire span remains the same as in Ladner-Fisher.

Buffers needed in both cases: K-S, L-F

Computer Arithmetic


Kogge stone adder

Kogge-Stone Adder

Computer Arithmetic


Parallel prefix adders brent kung

Parallel Prefix Adders: Brent-Kung

  • Set the fan-out to one

  • Avoids explosion of wires (as in K-S)

  • Makes no sense in CMOS:

    • fan-out = 1 limit is arbitrary and extreme

    • much of the capacitive load is due to wire (anyway)

  • It is more efficient to insert buffers in L-F than to use B-K scheme

Computer Arithmetic


Brent kung adder

Brent-Kung Adder

Computer Arithmetic


Parallel prefix adders han carlson

Parallel Prefix Adders: Han-Carlson

  • Is a hybrid synthesis of L-F and K-S

  • Trades increase in logic depth for a reduction in fan-out:

    • effectively a higher-radix variant of K-S.

    • others do it similarly by serializing the prefix computation at the higher fan-out nodes.

  • Others, similarly trade the logical depth for reduction of fan-out and wire.

Computer Arithmetic


Parallel prefix adders variety of possibilities3

Parallel Prefix Adders: variety of possibilities

from: Knowles

bounded by L-F and K-S at ends

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 1999

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

Following rules are used:

  • Lateral wires at the jth level span 2j bits

  • Lateral fan-out at jth level is power of 2 up to 2j

  • Lateral fan-out at the jth level cannot exceed that a the (j+1)th level.

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 19991

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

  • The number of minimal depth graphs of this type is given in:

  • at 4-bits there is only K-S and L-F, afterwards there are several new possibilities.

Computer Arithmetic


Parallel prefix adders variety of possibilities4

Parallel Prefix Adders: variety of possibilities

example of a new 32-bit adder [4,4,2,2,1]

Knowles 1999

Computer Arithmetic


Parallel prefix adders variety of possibilities5

Parallel Prefix Adders: variety of possibilities

Knowles 1999

Example of a new 32-bit adder [4,4,2,2,1]

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 19992

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

  • Delay is given in terms of FO4 inverter delay: w.c.

    (nominal case is 40-50% faster)

  • K-S is the fastest

  • K-S adders are wire limited (requiring 80% more area)

  • The difference is less than 15% between examined schemes

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 19993

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

Conclusion

  • Irregular, hybrid schmes are possible

  • The speed-up of 15% is achieved at the cost of large wiring, hence area and power

  • Circuits close in speed to K-S are available at significantly lower wiring cost

Computer Arithmetic


Vlsi arithmetic lecture 6

VLSI ArithmeticLecture 6

Prof. Vojin G. Oklobdzija

University of California

http://www.ece.ucdavis.edu/acsel


Review2

Review

Lecture 5


Prefix adders and parallel prefix adders1

Prefix Addersand Parallel Prefix Adders


Vlsi arithmetic adders multipliers

from: Ercegovac-Lang

Computer Arithmetic


Prefix adders1

Prefix Adders

Following recurrence operation is defined:

(g, p)o(g’,p’)=(g+pg’, pp’)

such that:

(g0, p0)

i=0

Gi, Pi =

(gi, pi)o(Gi-1, Pi-1 )

1 ≤ i ≤ n

ci+1 = Gi

for i=0, 1, ….. n

(g-1, p-1)=(cin,cin)

c1 = g0+ p0 cin

This operation is associative, but not commutative

It can also span a range of bits (overlapping and adjacent)

Computer Arithmetic


Parallel prefix adders s knowles 19991

Parallel Prefix Adders: S. Knowles 1999

operation is associative: h>i≥j≥k

operation is idempotent: h>i≥j≥k

produces carry: cin=0

Computer Arithmetic


Vlsi arithmetic adders multipliers

from: Ercegovac-Lang

Computer Arithmetic


Parallel prefix adders variety of possibilities6

Parallel Prefix Adders: variety of possibilities

from: Ercegovac-Lang

Computer Arithmetic


Parallel prefix adders variety of possibilities7

Parallel Prefix Adders: variety of possibilities

from: Ercegovac-Lang

Computer Arithmetic


Parallel prefix adders variety of possibilities8

Parallel Prefix Adders: variety of possibilities

from: Ercegovac-Lang

Computer Arithmetic


Kogge stone adder1

Kogge-Stone Adder

Computer Arithmetic


Brent kung adder1

Brent-Kung Adder

Computer Arithmetic


Hybrid bk ks adder1

Hybrid BK-KS Adder

Computer Arithmetic


Vlsi arithmetic adders multipliers

Pyramid Adder:M. Lehman, “A Comparative Study of Propagation Speed-up Circuits in Binary Arithmetic Units”, IFIP Congress, Munich, Germany, 1962.

Computer Arithmetic


Parallel prefix adders ladner fisher1

Parallel Prefix Adders: Ladner-Fisher

Exploits associativity, but not idempotency.

Produces minimal logical depth

Computer Arithmetic


Parallel prefix adders ladner fisher 16 8 4 2 11

Parallel Prefix Adders: Ladner-Fisher(16,8,4,2,1)

Two wires at each level. Uniform, fan-in of two.

Large fan-out (of 16; n/2); Large capacitive loading combined with the long wires (in the last stages)

Computer Arithmetic


Parallel prefix adders kogge stone1

Parallel Prefix Adders: Kogge-Stone

Exploits idempotency to limit the fan-out to 1.

Dramatic increase in wires. The wire span remains the same as in Ladner-Fisher.

Buffers needed in both cases: K-S, L-F

Computer Arithmetic


Parallel prefix adders brent kung1

Parallel Prefix Adders: Brent-Kung

  • Set the fan-out to one

  • Avoids explosion of wires (as in K-S)

  • Makes no sense in CMOS:

    • fan-out = 1 limit is arbitrary and extreme

    • much of the capacitive load is due to wire (anyway)

  • It is more efficient to insert buffers in L-F than to use B-K scheme

Computer Arithmetic


Two parallel prefix adder structures

Two Parallel Prefix Adder Structures

Han-Carlson

Kogge-Stone

  • log(bits) + 1 carry stages

  • Reduced Wiring and Gates

  • log(bits) carry stages

  • Extra Wiring

Computer Arithmetic


Parallel prefix adders han carlson1

Parallel Prefix Adders: Han-Carlson

  • Is a hybrid synthesis of L-F and K-S

  • Trades increase in logic depth for a reduction in fan-out:

    • effectively a higher-radix variant of K-S.

    • others do it similarly by serializing the prefix computation at the higher fan-out nodes.

  • Others, similarly trade the logical depth for reduction of fan-out and wire.

Computer Arithmetic


Parallel prefix adders variety of possibilities9

Parallel Prefix Adders: variety of possibilities

from: Knowles

bounded by L-F and K-S at ends

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 19994

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

Following rules are used:

  • Lateral wires at the jth level span 2j bits

  • Lateral fan-out at jth level is power of 2 up to 2j

  • Lateral fan-out at the jth level cannot exceed that a the (j+1)th level.

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 19995

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

  • The number of minimal depth graphs of this type is given in:

  • at 4-bits there is only K-S and L-F, afterwards there are several new possibilities.

Computer Arithmetic


Parallel prefix adders variety of possibilities10

Parallel Prefix Adders: variety of possibilities

example of a new 32-bit adder [4,4,2,2,1]

Knowles 1999

Computer Arithmetic


Parallel prefix adders variety of possibilities11

Parallel Prefix Adders: variety of possibilities

Knowles 1999

Example of a new 32-bit adder [4,4,2,2,1]

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 19996

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

  • Delay is given in terms of FO4 inverter delay: w.c.

    (nominal case is 40-50% faster)

  • K-S is the fastest

  • K-S adders are wire limited (requiring 80% more area)

  • The difference is less than 15% between examined schemes

Computer Arithmetic


Parallel prefix adders variety of possibilities knowles 19997

Parallel Prefix Adders: variety of possibilitiesKnowles 1999

Conclusion

  • Irregular, hybrid schmes are possible

  • The speed-up of 15% is achieved at the cost of large wiring, hence area and power

  • Circuits close in speed to K-S are available at significantly lower wiring cost

Computer Arithmetic


Possibilities for further research

Possibilities for Further Research

  • The logical depth is important (Knowles was right)

  • The fan-out is less important than fan-in (Knowles was wrong):

    • It is possible to examine a variety of topologies with restricted and varied fan-in.

  • Driving strength and Logical Effort rules were overlooked and at least neglected:

    • It is possible to create number of topologies taking LE rules into account.

    • It is further possible to combine the rules with compound domino implementation taking advantage of two different rules governing “dynamic” and “static”.

  • It is still possible to produce a better adder !

Computer Arithmetic


Other types of adders

Other Types of Adders

Computer Arithmetic


Conditional sum adder

Conditional Sum Adder

J. Sklansky, “Conditional-Sum Addition Logic”, IRE Transactions on Electronic

Computers, EC-9, p.226-231, 1960.


Conditional sum adder1

Conditional Sum Adder

from: Ercegovac-Lang

Computer Arithmetic


Conditionalsum adder

ConditionalSum Adder

Computer Arithmetic


Conditional sum adder2

Conditional Sum Adder

from: Ercegovac-Lang

Computer Arithmetic


Conditional sum adder3

Conditional Sum Adder

from: Ercegovac-Lang

Computer Arithmetic


Conditional sum adder4

Conditional Sum Adder

Computer Arithmetic


Carry select adder

Carry-Select Adder

O. J. Bedrij, “Carry-Select Adder”, IRE Transactions on Electronic Computers, June

1962, p.340-34


Carry select sum adder

Carry-Select Sum Adder

from: Ercegovac-Lang

Computer Arithmetic


Carry select adder1

Carry-Select Adder

Addition under assumption of Cin=0 and Cin =1.

Computer Arithmetic


Carry select adder combining two 32 b vbas in select mode

Carry Select Adder:combining two 32-b VBAs in select mode

Delay =DVBA32+ DMUX

Computer Arithmetic


Carry select adder2

Carry-Select Adder

O.J. Bedrij, IBM Poughkeepsie, 1962

Computer Arithmetic


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