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Lect10: Hardware Architecture of 80386

Lect10: Hardware Architecture of 80386. 386 DX Microprocessor. Flexible 32-bit Microprocessor Optimized for System Performance Pipelined Instruction Execution On-chip Address Translation Caches Dynamic Bus Sizing

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Lect10: Hardware Architecture of 80386

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  1. Lect10: Hardware Architecture of 80386

  2. 386 DX Microprocessor • Flexible 32-bit Microprocessor • Optimized for System Performance • Pipelined Instruction Execution • On-chip Address Translation Caches • Dynamic Bus Sizing • CHMOS(Complementary High-Performance Metal-Oxide-Semiconductor) III and CHMOS IV Technology • approximately 275,000 Transistors • more than twice that of the 80286 • almost 10 times that of the 8086 • 132-pin Pin Grid Array (PGA) package • See fig 9.2 : pin layout • See fig 9.2 (b) : signal pin numbering • 80386SX : 100-lead Plastic quad flat package(PQFP) - surface mount installation

  3. Interfaces of the 80386DX • Block Diagram of the 80386 • See Fig 9.3 on page 376 • Four interfaces • Memory/IO interface • Interrupt Interface • DMA Interface • Coprocessor Interface • Signals of the 80386DX • See Fig. 9.4 on page 377 • Memory/IO Interface • Address Bus A31 - A2 • Real address mode : only use 20 lines (A19 - A2) • Protected mode : use 32 lines • A0 - A1 : byte enable output • I/O address space : 64 K bytes A2 through A31 and the

  4. Data Bus: D31 - D0 • Bi-directional Bus • Dynamic Bus size : BS16 input • BE0 : D0 - D7 BE1 : D8 - D15 BE2 : D16 - D23 BE3 : D24 - D31 • Memory I/O Control • M/IO : memory/ input-output indication • W/R : write/read indication • D/C : data/control indication

  5. Bus Cycle Control Signals • ADS (Address status) • indicates that M/IO, D/C, W/R, BE, and ADDR are all stable • READY (Transfer Acknowledge) • NA (Next address) • Bus Interface control • LOCK (Bus lock indication) • Interrupt Interface • INTR (Interrupt request) • NMI (Non-maskable Interrupt) • RESET (System reset) • DMA Interface • HOLD (Bus hold request) • HLDA (Bus hold acknowledge) • Coprocessor Interface • PEREQ (Coprocessor request) • BUSY (Coprocessor busy) • ERROR (Coprocessor error)

  6. System Clock • CLK2 : Clock input • twice the frequency of the microprocessor : 32MHz(16MHz), 66MHz (33MHz) • See Fig 9.9 on page 384 • Hardware Organization of the Memory Address Space • Physical Memory space : 4GB • SW Viewpoint: organized ad individual byte over the address range form 00000000H through FFFFFFFFH • HW Organization: See fig 9.20 on page 393 • No Alignment • Bus State and Bus Cycle • Bus cycle: minimum two processor clock periods (two bus states: T states) - T1 and T2 • T state: a processor clock period (twice the period of the CLK2) • Non-pipelined and Pipelined Bus Cycle

  7. Non-pipelined Bus Cycle • Two T states(T1 and T2) • See Fig 9.10 • Pipelined Bus Cycle • See Fig 9.11

  8. READ and WRITE Bus Cycle Timing • Bus Cycles • read from memory space locked read from memory space write to memory space locked write to memory space read from I/O space write to I/O space interrupt acknowledge indicate halt or indicate shutdown • Non-pipelined Read Cycle Timing • See Fig 9.14, 9.15 • Non-pipelined Write Cycle Timing • See Fig 9.16, 9.17 • Pipelined Read- and Write-cycle timing • See Fig 9.18

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