SYEN 3330 Digital Systems

1. SYEN 3330 Digital Systems Chapter 9 – Part 2 SYEN 3330 Digital Systems

2. Overview of Chapter 9 – Part 2 • RAM Integrated Circuits • Dynamic RAM • Array of RAM Integrated Circuits • Arrays of Static and Dynamic RAMs SYEN 3330 Digital Systems

3. Dynamic RAM (DRAM) • Basic Principle: Storage of information on capacitors. • Charge and discharge of capacitor to change stored value • Use of transistor as “switch” to: • Store charge • Charge or discharge • See Figure 9-12 in text for circuit, hydraulic analogy, and logical model. SYEN 3330 Digital Systems

4. Dynamic RAM (DRAM) • Block Diagram – See Figure 9-14 in text • Refresh Controller and Refresh Counter • Read and Write Operations • Application of row address • Application of column address • Why is the address split? • Why is the row address applied first? • Timing – See Figure 9-15 in text SYEN 3330 Digital Systems

5. Data In Decoder A1 D-In A0 R/W D3 D-Out CS A1 D-In A0 R/W D-Out D2 CS A1 D-In A0 R/W D-Out D1 CS A1 D-In A0 R/W D0 D-Out CS A3 S1 A2 S0 Data Out A1 A0 R/W Making Larger Memories SYEN 3330 Digital Systems

6. Data In 3 2 1 0 A1 D-In A0 R/W D-Out CS A1 D-In A0 R/W D-Out CS A1 D-In A0 R/W D-Out CS A1 A1 D-In A0 A0 R/W R/W D-Out CS CS Data Out 3 2 1 0 Making Wider Memories SYEN 3330 Digital Systems