CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital Systems Lecture 10a

1. W’05 CS M51A/EE M16 Winter’05 Section 1 Logic Design of Digital SystemsLecture 10a February 16 Yutao He yutao@cs.ucla.edu 4532B Boelter Hall http://courseweb.seas.ucla.edu/classView.php?term=05W&srs=187154200

2. Outline • Administrative Matters • Arithmetic modules Wrap-up • Midterm Sneak Preview • Q & A Sessions

3. Administrative Matters • Homework #6 • Will be self-graded • You do not need to turn it in • The solution will be posted tonight • You’d better try it hard prior to checking with the solution • Homework #4 • Is graded

4. Arithmetic Modules: Overview • Types: • Half/Full Adders • Binary 1-bit • Binary n-bit • 1-digit full adder in other radix systems • Arithmetic Logic Units (ALUs) • Comparators • n x m combinational Multipliers • Basic Questions: • Inputs/outputs • High-level/binary-level functions • Implementation • Delays

5. x y carry_in sum carry-out 1-Bit Full Adder sum = x  y  c_in c_out = xy + (x  y) c_in 1-bit Full Adder (FA) High-Level Function: Binary-Level Function:

6. n-bit Full Adder

7. For 2’s Comp: - No change For 1’s Comp: - Carry wrap-around n-bit Full Adder for Signed Integers

8. High-Level Language Program z = x + y; Compiler Assembly Language Program ADC Y Assembler Machine Language Program 0001 0100 0010 1000 0000 0000 1001 0010 Opcode Operand R R R CPU Control Signals Controller ALU Status Signals How A Computer Computes

9. ALU (Cont’d)

10. 10010011 01001001 0 0 f2f1f0 = 001 1 Kx = 0 Ky = 0 KMX = 1 c0 = 0 0 ALU - An Example x = 10010011 y = 01001001 z = x+y? 1 0 0 0 11011100

11. nxm Multiplier for Positive Integer • Inputs/Outputs: • the multiplicand (n bits): 0  x  2n - 1 • the multiplier (m bits): 0  y  2m - 1 • the product: (n+m bits): 0  z  (2n - 1)(2m - 1) • The high-level function:

12. 8x6 Multiplication Bit Matrix

13. An Implementation of 8x6 Multiplier

14. The Delay of 8x6 Multiplier

15. Midterm Logistics • Date and Time: • 2:00pm- 3:50pm • February 18 (Friday), 2005 • Location: • Math Science 5200 • Extra Office Hours: • February 16 (Wednesday): 6-8pm 4750 BH • February 17 (Thursday): 7-8pm 4750BH • Policy: • Close-book and closed note • May bring two-page single-sided 8.5’x11’ cheat sheet • Calculator is allowed • Coverage: • Chapters 1 - 6, 10, and Handout Note #1

16. Material Won’t Be Covered • uVHDL: 2.6, 3.11, 4.5 • Power dissipation and noise margins: 3.5 • Multiplexers: part of 3.2.6, 6.4 • Carry-Lookahead Adder: part of 10.1, part of 10.2 • ALU Networks: part of 10.4 • Comparator Networks:10.5 • Networks with standard arithmetic modules:10.7

17. Design Combinational Arithmetic Analysis High-Level Logic Binary-Level Circuit What We Have Learned - Representation - Minimization - Implementation - Delay - Load Factor - Fanout Factor - Size - Level - Words Problem - Number Systems - Encoding Scheme

18. Decide: Inputs,Output, Function Common Sense, Educated Guess Step 1: Number Systems, Standard Select: Encoding Scheme Step 2: Fill in: Truth Table Boolean Operations Step 3: S. Algebra CSP, CPS Write: Canonical S. E. Construct: K-Map. Step 4: Boolean Identities Simplify: S. E. Simplify: By Grouping Step 5: Carefulness Implement: w/ 2-level Gate networks Primitive Logic Gates, PLAs Step 6: Transform: other gate types, multi-level Step 7: Mixed-Logic, etc. Verify: correctness, timing Step 8: Analysis Road-Map of Combinational Systems Adjacency Condition

19. - Positive - Negative Base 10 Number Systems and Conversions Base 8 Base 16 Base 2 - Function Equivalence Specification Truth Table K-Map S. E. - Boolean Algebra - K-Map - Quine-McCluskey Algorithm Minimization Implementation - Gate networks (Universal Set) + two-level + multiple-level - PLAs AND-OR NAND-NAND OR-AND NOR-NOR Analysis - Functional Analysis -> Debugging - Delays: H-> L and L->H - Fan-out/Fan-in Things You Should Know Well

20. Midterm Sneak Preview • Philosophy • Test your digital fluency in two aspects: • Grasp of basic theories and techniques • Hands-on skills of analyzing and designing a combinational digital system • Format: • Design • Analysis: debugging, etc. • Length: • Will have 8 to 9 problems • Points are assigned according to the estimated difficulty of the problems • Style: • Q&A

21. Rehearsal Example 1 • Given a bit vector X = 10011 • Find out the value of y = - (9x/2)+3 in 2’s complement system • Use only addition, complementation, shift, and range extension

22. 4-bit Binary FA 1101 To Be Designed In BCD code, it should be: 0001 0011 -> 13 Rehearsal Example 2 • Design a 1-digit decimal full adder (radix-10 adder) using the 4-bit Binary Full Adder and other glue logics 0101 1000

23. c3 z3 z2 z1 z0 cout s3 s2 s1 s0 4-bit Binary FA ……… ……… ……… ……… To Be Designed ……… ……… Rehearsal Example 2 - Cont. • Key questions: • What’s the largest number 1-digit decimal adder can represent? • When do outputs of binary adders need to be changed? • Basic Approach: • Inputs: • Outputs: • Functions: Truth Table 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 0 - - - - - 1 1 1 1 1 - - - - -

24. Rehearsal Example 3 • Design a circuit that calculate the following equation: y = x^2-x+1 where x > 0 and < 4 • Use two-level NAND-NAND network • Use two-level NOR-NOR network • Use a PLA

25. Summary • Arithmetic modules • Midterm Review

26. Next Lecture • The Midterm Sleep well, Study Hard, and Good luck!