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Timing Event-driven simulation

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Sources

- A. Deway, Analysis and Design of Digital
- Systems with VHDL,
- Chapters 15, VHDL Technology
- M. Abramovici, M. Breuer, A. Friedman
- Chapter 3.10, Gate-Level Event Driven Simulation
- P. Ashenden, The Designer’s Guide to VHDL,
- Chapter 5.3
- Signal Attributes
- Delta Delays
- Transport and Inertial Delay Mechanisms

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Timing Characteristics of Combinational Circuits

LUT

LUT

LUT

tp LUT

tp routing

Total propagation delay through combinational logic

- Combinational Circuits Are Characterized by Propagation Delays
- through logic components (gates, LUTs)
- through interconnects (routing delays)

ECE 545 – Introduction to VHDL

Timing Characteristics of Combinational Circuits (2)

- Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components
- Number of logic levels is the number of logic components (gates, LUTs) the signal propagates through

- Routing Delays Depend on:
- Length of interconnects
- Fanout

ECE 545 – Introduction to VHDL

Timing Characteristics of Combinational Circuits (3)

LUT

LUT

LUT

LUT

- Fanout – Number of Inputs Connected to One Output
- Each inputs has its capacitance
- Fast switching of outputs with high fanout requires higher currents and strong drivers

ECE 545 – Introduction to VHDL

Timing Characteristics of Combinational Circuits (4)

- In Current Technologies Routing Delays Make 50-70% of the Total Propagation Delays

ECE 545 – Introduction to VHDL

Timing Characteristics of Sequential Circuits (1)

- Timing Features of Flip-flops
- Setup time tS – minimum time the input has to be stable before the rising edge of the clock
- Hold time tH – minimum time the input has to be stable after the rising edge of the clock
- Propagation delay tP – time to propagate input to output after the rising edge of the clock

ECE 545 – Introduction to VHDL

Timing Characteristics of Sequential Circuits (2)

clk

clk

D

tS

tH

D

Q

Q

tP

Input D must remain

stable during

this interval

Input D can freely

change during

this interval

ECE 545 – Introduction to VHDL

Critical Path (1)

tP logic

out

in

clk

D

D

Q

Q

tCritical = tP FF + tPlogic + tS FF

- Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers

ECE 545 – Introduction to VHDL

Critical Path (2)

- Min. Clock Period = Length of The Critical Path
- Max. Clock Frequency = 1 / Min. Clock Period

ECE 545 – Introduction to VHDL

Clock Jitter

- Rising Edge of The Clock Does Not Occur Precisely Periodically
- May cause faults in the circuit

clk

ECE 545 – Introduction to VHDL

Clock Skew

out

in

clk

delay

out

in

D

D

Q

Q

D

D

Q

Q

clk

delay

- Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same Time

ECE 545 – Introduction to VHDL

Dealing With Clock Problems

- Use Only Dedicated Clock Nets for Clock Signals
- Do Not Put Any Logic in Clock Nets

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Physical data types

Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types.

TIME is the only predefined physical data type.

Value of the physical data type is called a physical literal.

ECE 545 – Introduction to VHDL

Time values (physical literals) - Examples

7 ns

1 min

min

10.65 us

10.65 fs

Numeric value

Space

Unit of time

(dimension)

ECE 545 – Introduction to VHDL

TIME values

Numeric value can be an integer or

a floating point number.

Numeric value is optional. If not given, 1 is

implied.

Numeric value and dimension MUST be

separated by a space.

ECE 545 – Introduction to VHDL

Units of time

Unit Definition

Base Unit

fs femtoseconds (10-15 seconds)

Derived Units

ps picoseconds (10-12 seconds)

ns nanoseconds (10-9 seconds)

us microseconds (10-6 seconds)

ms miliseconds (10-3 seconds)

sec seconds

min minutes (60 seconds)

hr hours (3600 seconds)

ECE 545 – Introduction to VHDL

Values of the type TIME

Value of a physical literal is defined in terms

of integral multiples of the base unit, e.g.

10.65 us = 10,650,000,000 fs

10.65 fs = 10 fs

Smallest available resolution in VHDL is 1 fs.

Smallest available resolution in simulation can be

set using a simulator command or parameter.

ECE 545 – Introduction to VHDL

Arithmetic operations on values of the type TIME

Examples:

7 ns + 10 ns = 17 ns

1.2 ns – 12.6 ps = 1187400 fs

5 ns * 4.3 = 21.5 ns

20 ns / 5ns = 4

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Propagation delay in VHDL - Example

entity MAJORITY is

port

(A_IN, B_IN, C_IN : in STD_LOGIC;

Z_OUT : out STD_LOGIC);

end MAJORITY;

architecture DATA_FLOW of MAJORITY is

begin

Z_OUT <= (not A_IN and B_IN and C_IN) or

(A_IN andnot B_IN and C_IN) or

(A_IN and B_IN and not C_IN) or

(A_IN and B_IN and C_IN) after 20 ns;

end DATA_FLOW;

ECE 545 – Introduction to VHDL

Propagation delay - Example

ECE 545 – Introduction to VHDL

MLU: Block Diagram

ECE 545 – Introduction to VHDL

MLU - Architecture Body – Example 1

begin

A1<=not A after 6 nswhen (NEG_A='1') else

Aafter 5 ns;

B1<=not B after 6 nswhen (NEG_B='1') else

Bafter 5 ns;

Y<=not Y1 after 6 nswhen (NEG_Y='1') else

Y1after 5 ns;

MUX_0<=A1 and B1after 3 ns;

MUX_1<=A1 or B1after 3 ns;

MUX_2<=A1 xor B1after 4 ns;

MUX_3<=A1 xnor B1after 5 ns;

L<=L1 & L0;

with (L) select

Y1<=MUX_0 after 7 nswhen "00",

MUX_1 after 6 nswhen "01",

MUX_2 after 8 nswhen "10",

MUX_3 after 7 nswhen others;

end MLU_DATAFLOW;

ECE 545 – Introduction to VHDL

MLU - Architecture Body – Example 2

begin

A1<=not A after MUX2_delaywhen (NEG_A='1') else

Aafter MUX_2_delay;

B1<=not B after MUX2_delaywhen (NEG_B='1') else

Bafter MUX2_delay;

Y<=not Y1 after MUX2_delaywhen (NEG_Y='1') else

Y1after MUX2_delay;

MUX_0<=A1 and B1after GATE_delay;

MUX_1<=A1 or B1after GATE_delay;

MUX_2<=A1 xor B1after XOR_delay;

MUX_3<=A1 xnor B1after XOR_delay;

L<=L1 & L0;

with (L) select

Y1<=MUX_0 after MUX4_delaywhen "00",

MUX_1 after MUX4_delaywhen "01",

MUX_2 after MUX4_delaywhen "10",

MUX_3 after MUX4_delaywhen others;

end MLU_DATAFLOW;

ECE 545 – Introduction to VHDL

Delay constants

constant MUX2_delay : time := 5 ns;

constant GATE_delay : time := 3 ns;

constant XOR_delay : time := 4 ns;

constant MUX4_delay : time := 7 ns;

Can be defined in the declarative portion

of the architecture or in the package

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Inertial delay model

Short pulses (spikes) are not passed to the

outputs of logic gates due to the inertia of

physical systems.

Logic gates behave like low pass filters and

effectively filter out high frequency input

changes as if they never occurred.

ECE 545 – Introduction to VHDL

VHDL-87 Inertial delay model

Any input signal change that does not persist

for at least a propagation delay of the device

is not reflected at the output.

inertial delay (pulse rejection limit) = propagation delay

ECE 545 – Introduction to VHDL

VHDL-93 Enhanced inertial delay model

VHDL-93 allows the inertial delay model to be declared

explicitly as well as implicitly.

Explicitly:

Z_OUT <= inertial (not A_IN and B_IN and C_IN) or

(A_IN andnot B_IN and C_IN) or

(A_IN and B_IN and not C_IN) or

(A_IN and B_IN and C_IN) after 20 ns;

Implicitly:

Z_OUT <= (not A_IN and B_IN and C_IN) or

(A_IN andnot B_IN and C_IN) or

(A_IN and B_IN and not C_IN) or

(A_IN and B_IN and C_IN) after 20 ns;

ECE 545 – Introduction to VHDL

VHDL-93 Enhanced inertial delay model

VHDL-93 allows inertial delay, also called

a pulse rejection limit, to be different from the

propagation delay.

SIG_OUT <= reject 5 ns inertialnot SIG_IN after 7 ns;

ECE 545 – Introduction to VHDL

Transport delay model

With a transport delay model, all input signal

changes are reflected at the output, regardless of

how long the signal changes persist.

Transport delay model must be declared explicitly using the

keyword transport.

Inertial delay model is a default delay model because it

reflects better the actual behavior of logic components.

Transport delay model is used for high-level modeling.

ECE 545 – Introduction to VHDL

Transport delay model - Example

SIG_OUT <= transportnot SIG_IN after 7 ns

ECE 545 – Introduction to VHDL

Other delay models

Rise and Fall delays

- a different delay for a transition 0→1

and a transition 1→0

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Event list as a linked list structure

List of events scheduled

to occur at time tq

time

signal

new value

ECE 545 – Introduction to VHDL

Event list as an array – Timing wheel

List of events scheduled

to occur at time tc

time

signal

new value

ECE 545 – Introduction to VHDL

Notation

(i, vi’) – an entry of the event list associated with the time t indicating that at the time t the value of signal i is scheduled to be set to vi’

v(i) – current value at the output of gate i

d(i) – nominal delay of gate i

ECE 545 – Introduction to VHDL

Top-level algorithm

while (event list not empty)

begin

t = next time in list

process entries for time t

end

ECE 545 – Introduction to VHDL

Process entries for time t - Basic version

Activated = Ø /* set of activated gates = empty set */

For every entry (i, vi’) pending at the current time t

if vi’ ≠ v(i) then

begin /* it is indeed an event */

v(i) = vi’ /* update value of signal i */

for every j on the fanout list of i

begin

update input values of j

add j to Activated

end

end

For every j Activated

begin

vj’ = evaluate(j)

schedule (j, vj’) for time t+d(j)

end

ECE 545 – Introduction to VHDL

Notation

lsv(j) – last scheduled value of j

lst(j) – last scheduled time of j = time of the last event scheduled for signal j

ECE 545 – Introduction to VHDL

Process entries for time t – True events only version – Two-pass algorithm

Activated = Ø /* set of activated gates = empty set */

For every entry (i, vi’) pending at the current time t

if vi’ ≠ v(i) then

begin /* it is indeed an event */

v(i) = vi’ /* update value of signal i */

for every j on the fanout list of i

begin

update input values of j

add j to Activated

end

end

For every j Activated

begin

vj’ = evaluate(j)

if vj’ ≠ lsv(j) then

begin

schedule (j, vj’) for time t+d(j)

lsv(j) = vj’

end

end

ECE 545 – Introduction to VHDL

Process entries for time t – True events only version – One-pass algorithm

For every entry (i, vi’) pending at the current time t

begin

for every j on the fanout list of i

begin

update input values of j

vj’ = evaluate(j)

if vj’ ≠ lsv(j) then

begin

t’ = t + d(j)

if t’ = lst(j) then

cancel event (j, lsv(j)) at time t’

schedule (j, vj’) for time t’

lsv(j) = vj’

lst(j) = t’

end

end

end

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Delta delay

A propagation delay of 0 time units is

equivalent to omitting the after clause and is

called a delta delay.

Used for functional simulation.

ECE 545 – Introduction to VHDL

Two-dimensional aspect of time

ECE 545 – Introduction to VHDL

Top-level algorithm

while (event list not empty)

begin

t = next time in list

process entries for time t

end

If next time in list

= previous time

then the previous

iteration of the

loop has advanced

time by one

delta delay

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Transaction vs. Event

T5 = T1+20 ns

Z_OUT transactions

(‘0’, T1 + 20 ns) (‘1’, T2 + 20 ns) (‘0’, T3 + 20 ns)

(‘1’, T2 + 20 ns) (‘0’, T3 + 20 ns)

Z_OUT events

ECE 545 – Introduction to VHDL

Properties of signals

Signals represent a time-ordered list of values

denoting past, present and future values.

This time history of a signal is called a waveform.

A value/time pair (v, t) is called a transaction.

If a transaction changes value of a signal, it is

called an event.

ECE 545 – Introduction to VHDL

ECE 545 – Introduction to VHDL

Signal attributes (1)

S’transaction - a signal of type bit that changes value from ‘0’ to ‘1’ or vice versa each time there is a transaction on S.

S’event - True if there is an event on S in the current simulation cycle, false otherwise.

S’active – True if there is a transaction on S in a given simulation cycle, false otherwise.

ECE 545 – Introduction to VHDL

Signal attributes (2)

S’last_event - The time interval since the last event on S.

S’last_active - The time interval since the last transaction on S.

S’last_value – The value of S just before the last event on S.

ECE 545 – Introduction to VHDL

Signal attributes (3)

S’delayed(T) - A signal that takes on the same value as S, but is delayed by time T.

S’stable(T) - A Boolean signal that is true if there has been no event on S in the time interval T up to the current time, otherwise false.

S’quiet(T) – A Boolean signal that is true if there has been no transaction on S in the time interval T up to the current time, otherwise false.

ECE 545 – Introduction to VHDL

Detecting setup time violation

if clk’event and clk=‘1’ then

assertd’last_event >= setup_time

report “Setup time violation”

ECE 545 – Introduction to VHDL

Timing simulation after synthesis

ECE 545 – Introduction to VHDL

Synthesis process

- Simulation before synthesis is used to verify circuit functionality and may differ from the one after synthesis
- Synthesis tool generates SDF (Standard Delay Format) as a standard delay file and the netlist for synthesized VHDL code with delays.
- Generated netlist contains many component instantiation statements with library references

ECE 545 – Introduction to VHDL

SDF file

A part of the SDF file is shown below.

It indicates XOR gate delays (low to high, high to low) of minimum, typical and worst case timing

( DELAYFILE

( CELL( CELLTYPE “XOR”)

( INSTANCE U34.Z_VTX)

( DELAY( INCREMENT

( DEVICE 01

(0.385090:0.385090:0.385090)(0.235177: 0.235177: 0.235177)

) ) ) )

ECE 545 – Introduction to VHDL

Netlist from the synthesis tool

U30 : MUX21L port map( Z => n71, A => n67, B => n68, S => n69);

U31 : EN port map( Z => n67, A => D1, B => D0);

U32 : IV port map( Z => n68, A => n67);

U33 : EOP port map( Z => n69, A => D6, B => D7);

U34 : EO3 port map( Z => n70, A => D3, B => D2,

C => D4);

U35 : EO port map( Z => n72, A => D5, B => n70);

U36 : EOP port map( Z => XOR8, A => n72,

B => n71);

U37 : FA1A port map( S => n73, CO => n76, CI => D3, A => D2, B => FF);

U38 : EO3 port map( Z => n74, A => n68, B => n73,

C => D4);

U39 : EOP port map( Z => FF_COMB_OUT, A => D5, B => n74);

end structural;

library IEEE;

library TC200G;

use IEEE.std_logic_1164.all;

use TC200G.components.all;

entity CONSYN is

port( RSTn, CLK, D0, D1, D2, D3, D4, D5, D6, D7 : in std_logic; FF_OUT,

COMB_OUT, FF_COMB_OUT : out std_logic);

end CONSYN;

architecture structural of CONSYN is

signal XOR8, FF, n70, n71, n72, n73, n74, n75, n76, n67, n68, n69 : std_logic;

begin

FF_OUT <= FF;

COMB_OUT <= XOR8;

FF_reg : FD2 port map( Q => FF, QN => n75, D => XOR8, CP => CLK, CD => RSTn) ;

ECE 545 – Introduction to VHDL

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