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1. Microcontrollers Specially designed microprocessors It is small on chip computer Highly integrated chip includes all or most parts needed for controller A typical microcontroller has: bit manipulation easy and direct access to I/O quick and efficient interrupt processing Microcontroller drastically reduces design cost

2. Worldwide Microcontroller shipments - in millions of dollars -

3. Worldwide Microcontroller shipments - in millions -

4. Applications Appliances (microwave oven, refrigerators, television and VCRs, stereos) Computers and computer equipment (laser printers, modems, disk drives) Automobiles (engine control, diagnostics, climate control), Environmental control (greenhouse, factory, home) Instrumentation Aerospace Robotics, etc...

5. Flavors 4, 8, 16, or 32 bit microcontrollers specialized processors include features specific for communications, keyboard handling, signal processing, video processing, and other tasks.

6. Popular Microcontrollers 8048 (Intel) 8051 (Intel and others) 80c196 (MCS-96) 80186,80188 (Intel) 80386 EX (Intel) 65C02/W65C816S/W65C134S (Western Design Center) MC14500 (Motorola)

7. Popular Microcontrollers 68HC05 (Motorola) 68HC11 (Motorola and Toshiba) 683xx (Motorola) PIC (MicroChip) COP400 Family (National Semiconductor) COP800 Family (National Semiconductor) HPC Family (National Semiconductor) Project Piranha (National Semiconductor)

8. Popular Microcontrollers Z8 (Zilog) HD64180 (Hitachi) TMS370 (Texas Instruments) 1802 (RCA) MuP21 (Forth chip) F21 (Next generation Forth chip)

9. Programming Microcontrollers Machine/Assembly language Interpreters (Java, ...) Compilers (C, C++, ...) Fuzzy Logic and Neural Networks

10. Development Tools Simulators Resident Debuggers Emulators

11. Choosing microcontoller Technical support Development tools Documentation Purchasing more devices at one manufacturer (A/D, memory, etc.) Additional features (EEPROM, FLASH, LCD driver, etc.)

12. Microcontrollers Basic parts are: Central Processing Unit RAM EPROM/PROM/ROM or FLASH Memory I/O serial or/and parallel timers interrupt controller Optional parts are: Watch Dog Timer AD Converter LCD driver etc.

13. Intel 8051 A typical 8051 contains: CPU with Boolean processor 5 or 6 interrupts: 2 external, 2 priority levels 2 or 3 16-bit timer/counters programmable full-duplex serial port 32 I/O lines (four 8-bit ports) RAM ROM/EPROM in some models

14. Intel 8051: Pin Description VSS - Ground: 0V VCC - Power Supply P0.0-P0.7 - Port 0 Open drain, bi-directional I/O port Pins that have 1s written to them float and can be used as high-impedance inputs Multiplexed low-order address and data bus during accesses to external program and data memory

15. Intel 8051: Pin Description P2.0-P2.7 - Port 2 Bi-directional I/O port with internal pull-ups Pins that have 1s written to them float and can be used as high-impedance inputs. Port 2 emits high-order address byte during accesses to external program and data memory P3.0-P3.7 - Port 3 Bi-directional I/O port with internal pull-ups Pins that have 1s written to them float and can be used as high-impedance inputs. Port 3 serves the special features: RxD - Serial input port TxD - Serial output port INT0 - External interrupt INT1 - External interrupt T0 - Timer 0 external input T1 - Timer 1 external input WR - External data memory write strobe RD - External data memory read strobe

16. Intel 8051: Pin Description RST - Reset A high on this pin for two machine cycles resets the devices ALE - Address Latch Enable Output pulse for latching the low byte of address during an access to external memory PSEN - Program Store Enable Read strobe to external program memory EA - External Access Enable EA must be externally held low to enable device to fetch code from external memory locations. XTAL1 - Crystal 1 Input to the inverting oscillator amplifier and input to internal clock generator circuits XTAL2 - Crystal 2 Output from the inverting oscillator amplifier

17. Intel 8051: Pin Configurations Dual In-Line Package Plastic Lead Chip Carrier Plastic Quad Flat Pack

18. Intel 8051: Pin Configurations

19. Intel 8051: CPU Primary elements are: eight bit ALU with associated registers A, B, PSW and SP sixteen-bit Program Counter (PC) Data Pointer registers

20. Intel 8051: CPU The ALU can manipulate one-bit as well as eight-bit data types This features makes the 8051 especially well suited for controller-type applications A total of 51 separated operations move and manipulate three data types: Boolean (1-bit) Byte (8-bit) Address (16-bit)

21. Intel 8051: CPU Instruction types: Arithmetic Operations Logic Operations for Byte Variables Data Transfer Instructions Boolean Variable Manipulation Program Branching and Machine Control

22. Intel 8051: CPU There are eleven addressing modes: seven for data four for program sequence control Most operations allow several addressing modes, bringing total number of instructions to 111, encompassing 255 of the 256 possible 8-bit instruction opcodes 8051 instruction set fares well at both real-time control and data intensive algorithms

23. Intel 8051: Memory Organization Program memory is separate distinct from data memory Each memory type has a different addressing mechanism, different control signals, and a different functions Architecture supports several distinct “physical” address spaces functionally separated at the hardware level: On - chip program memory On - chip data memory Off - chip program memory Off - chip data memory On chip special function registers

24. Intel 8051: Memory Organization Program (Code) memory Holds the actual 8051 program that is to be run Limited to 64K may be found on-chip as ROM or EPROM may be stored completely off-chip in an external ROM or an external EPROM Flash RAM is also another popular method of storing a program Various combinations of these memory types may be used (e.g. 4 K on-chip and 64 KB off-chip)

25. Intel 8051: Memory Organization External RAM External RAM is any random access memory which is found off-chip External RAM is slower To increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction cycle To increment a 1-byte value stored in External RAM requires 4 instructions and 7 instruction cycles While Internal RAM is limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM up to 64K

26. Intel 8051: Memory Organization On-chip memory Two types: Internal RAM; and Special Function Register (SFR) memory Internal RAM is on-chip so it is the fastest RAM available Internal RAM is volatile, when the 8051 is reset this memory is cleared Special Function Registers (SFRs) are areas of memory that control specific functionality of the 8051 processor

27. Intel 8051: Memory Access PORT 2 : High byte of address held for the duration of read or write cycle PORT 0 : time multiplexed low byte of address with data byte Signal ALE: used to capture the address byte into an external latch

28. Intel 8051: Memory Access

29. Intel 8051: Program Memory Up to 64K of Program Memory PSEN: read strobe for all external program fetches PSEN: not activated for internal program fetches Depending on EA pin lowest bytes can be either in the on-chip ROM or in an external ROM

30. Intel 8051: Program Memory Boot address - 0x0000 Each interrupt is assigned a fixed location in Program Memory If interrupt is not going to used, its service location is available as general purpose Program Memory

31. Intel 8051: Program Memory Port 0 and Port 2 are dedicated to bus functions during external Program Memory fetches

32. Intel 8051: Data Memory Up to 64K Data Memory Access to Data memory use RD or WR to strobe the memory

33. Intel 8051: Data Memory Internal Memory Addresses are one byte wide - 128 bytes address space (256 - Intel 8052) Direct addressing higher then 0x7F access one memory space, indirect addressing higher then 0x7F access a different memory space Upper 128 and SFR space occupying same block of addresses, although they are physically separate entities

34. Intel 8051: Data Memory The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers R0 through R7 Two bits in the PSW selects register bank Register instructions are shorter The next 16 bytes form a block of bit-addressable space

35. Intel 8051: SFR SFRs are accessed as if they were normal Internal RAM SFR registers exist in the address range of 80h through FFh Each SFR has an address and a name

36. Intel 8051: SFR

37. Intel 8051: SFR Accumulator (A) Accumulator register B Register (B) Used during multiply and divide operations PSW Contains program status information Stack Pointer (SP) Eight bits wide Stack may reside anywhere in on chip RAM The Stack Pointer is initialized on 0x07 after a reset, and this causes stack to begin at location 0x08 Data Pointer(DPTR) Consist high byte (DPH) and low byte (DPL) It may be manipulated as a 16-bit register or as two independent 8-bit registers

38. Intel 8051: SFR Ports 0 to 3 (P0, P1, P2, P4) Latches of Port 0 to 3, respectively Serial Data Buffer (SDBF) It is actually two separated registers: receive and transmit buffer registers When data is moved to SBUF it goes to the transmit buffer When data is moved from SBUF it comes from the receive buffer Timer Registers (T1, T0) (TH1, TL1) (TH0, TL0) Counting Registers for Timer/Counter 1 and 0 Control Registers IP: Interrupt priority IE: Interrupt enable TMOD Timer/Counter mode TCON Timer/Counter control PCON Power control

39. Intel 8051: PSW Auxiliary Carry flag is used for BCD operations Flag 0 is available to user for general purposes The contest of (RS1, RS2) enable working register banks as follows: 00 - Bank 0 [0x00-0x07], 01 - Bank 1 [0x08-0x0f], 10 - Bank 2 [ 0x10-0x17], 11 - Bank 3 [0x18-0x1F]

40. Intel 8051: CPU Timing The internal clock generator defines the sequence of states that make up a machine cycle A machine cycle consists of 6 states, numbered S1 through S6 Each state time lasts for two oscillator periods Each state is then divided into a Phase 1 and Phase 2 half

41. Intel 8051: Port Structures Pseudo bi-directional I/O port structure On Port0 R2 is disabled except during bus operations (open-collector output) The address latch bit is updated by direct addressing instructions The value read is “OR-tied” function of Q1 and the external device To use a pin for input latch must be set

42. Intel 8051: Port Interfacing The output buffers of Ports 0, 1, 2 and 3 can each drive 4 LS TTL inputs Can be driven by open-collector and open-drain outputs 0-to-1 transitions will not be fast since there is little current pulling the pin up Port 0 output buffers can each drive 8 LS TTL inputs (external bus mode) As port pins PORT 0 requires external pull-ups to be able to drive any inputs bit

43. Intel 8051: Special Peripheral Functions There are few special needs common among control-oriented computer systems: keeping tracks of elapsed time maintaining a count of signal transitions measuring the precise width of input pulses communicating with other systems closely monitoring asynchronous external events

44. Intel 8051: Timers/Counters Two 16-bit Timer/Counter registers Timer: Register is incremented every machine cycle (1 machine cycle = 12 oscillator periods) Counter: Register is incremented in response to 1-to-0 transition at its corresponding external input pin (T0, T1) External input is sampled at S5P2 of every machine cycle When the samples show high in one cycle and low in the next, the count is incremented The new count value is appears in S3P1 of the following detection cycle Max count rate is 1/24 of oscillator frequency TMOD - Timer/Counter mode register TCON - Timer/Counter control register

45. Intel 8051: Timers/Counters GATE: Gating control when set C/T: Counter or Timer Selector M1 M0: 00: 8-bit Timer/Counter with 5-bit prescaler 01: 16-bit Timer/Counter 10: 8-bit auto reload Timer/Counter 11: (Timer0) TL0 is 8-bit Timer/Counter controlled by Timer0 control bits TH0 is 8-bit timer only controlled by Timer1 control bits 11: (Timer1) Timer/Counter is stopped

46. Intel 8051: Timers/Counters TF: Overflow flag Set by hardware on Timer/Counter overflow Cleared by hardware when processor vectors to interrupt routine TR: Run control bit Set/Cleared by software to turn Timer/Counter on/off IE: Interrupt Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed IT: Interrupt Type control bit Set/Cleared by software to specify falling edge/low level triggered external interrupts

47. Intel 8051: Timers/Counters

48. Intel 8051: Timers/Counters

49. Intel 8051: Timers/Counters

50. Intel 8051: Timers/Counters

51. Intel 8051: Serial Port Interface Full-duplex Serial port receive and transmit registers are both accessed at Special Function Register SBUF Writing to SBUF loads the transmit register Reading from SBUF accesses a physically separated receive register Four modes of operation In all four modes transmission is initiated by any instruction that uses SBUF as destination register Reception is initiated in Mode 0 by condition RI=0 and REN=1 In other modes by the incoming start bit if REN=1 SCON - Serial Port Control Register

52. Intel 8051: Serial Port Interface SM0 SM1: 00: Mode 0, Shift register, fosc//12 01: Mode 1, 8-bit UART, variable 10: Mode 2, 9-bit UART, fosc//32 or fosc//64 11: Mode 3, 9-bit UART, variable SM2: Enables multiprocessor features in Mode 2 and Mode 3 When the stop bit is received, the interrupt will be activated only if RB8=1 (9th bit =1) REN: Enables serial reception Set/Clear by software

53. Intel 8051: Serial Port Interface TB8: 9th data bit that will be transmitted in Mode2 and Mode3 Set/Clear by software RB8: 9th data bit that was received in Mode2 and Mode3 In Mode 1, if SM2=0, is the stop bit that was received TI: Transmit interrupt flag Set by hardware. Must be cleared by software RI: Receive interrupt flag Set by hardware. Must be cleared by software

54. Intel 8051: Serial Port Interface MODE 0: Serial data enters and exits through RXD TXD outputs shift clock 8 bits are transmitted/received: 8 data bits (LSB first) The baud rate is fixed at 1/12 oscillator frequency MODE 1: Serial data enters through RXD, exits through TXD 10 bits are transmitted/received: start bit(0), 8 data bits (LSB first), stop bit(1) On receive the stop bit goes into RB8 in SCON register The baud rate is variable

55. Intel 8051: Serial Port Interface MODE 2: Serial data enters through RXD, exits through TXD 11 bits are transmitted/received: start bit(0), 8 data bits (LSB first), a programmable 9th bit, stop bit(1) On transmit, the 9th bit is TB8 in SCON register On receive, the 9th bit goes into RB8 in SCON register The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency MODE 3: Same as MODE 2 in all respects except baud rate The baud rate is variable

56. Intel 8051: Serial Port Interface Mode 0 Baud Rate = Oscillator frequency/12 Mode 2 Baud Rate =[(2SMOD)/64]*Oscillator frequency SMOD is bit in Special Function Register PCON Mode 1 and Mode3 baud rate is determined by Timer 1 overflow rate Mode 1,3 Baud Rate =[(2SMOD)/32]* Timer 1 Overflow Rate Timer mode, auto-reload : Timer Overflow Rate=Oscillator frequency/[12*(256-TH1)]

57. Intel 8051: Serial Port Interface

58. Intel 8051: Interrupt Control EA: Enable/Disable all interrupts If EA=0 no interrupts will be acknowledged If EA=1 each interrupt source is individually enabled/disbled ES: Serial Port interrupt enable bit ET: Timer interrupt enabled bit EX: External interrupt enable bit

59. Intel 8051: Interrupt Control

60. Intel 8051: Interrupt Control External interrupts Level-activated or transition-activated depending on bits IT0, IT1 in register TCON The flags that generate these interrupts are IE0, IE1 in TCON Cleared by hardware if the interrupt was transition-activated if the interrupt was level-activated, external source controls request bits If external interrupt is level-activated, the external source has to hold request active, until the requested interrupt is actually generated. External source has to deactivate the request before interrupt service is completed, or else another interrupt will be generated

61. Intel 8051: Interrupt Control Timer interrupts Interrupts are generated by TF0 and TF1 in register TCON When a timer interrupt is generated, the flag that generated it is cleared by hardware when the service routine is vectored to Serial Port interrupt generated by the logical OR of bits RI and TI in register SCON

62. Intel 8051: Interrupt Control Priority bit=1: High Priority; Priority bit=0: Low Priority PS: Serial Port priority bit PT: Timer priority bit PX: External priority bit

63. Intel 8051: Interrupt Control A low-priority interrupt can be interrupted by a higher priority interrupt, but not by another low-priority interrupt A high priority interrupt cannot be interrupted by any other interrupt source If two requests are received simultaneously, the request of higher priority level is serviced If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced ``priority within level'' structure is only used to resolve simultaneous requests of the same priority level.

64. Intel 8051: Interrupt Control

65. Intel 8051: Interrupt Control The INT0 and INT1 levels are inverted and latched into the Interrupt Flags IE0 and IE1 at S5P2 of every machine cycle Serial Port flags RI and TI are set at S5P2 The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow If a request is active and conditions are right, a hardware subroutine call to the requested service routine will be the next instruction to be executed In a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles

66. Intel 8051: Reset The reset input is the RST pin, which has a Schmitt Trigger input Accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running The RST pin is sampled during S5P2 of every machine cycle While the RST pin is high, the port pins, ALE and PSEN are weakly pulled high Driving the ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state

67. Intel 8051: Reset

68. Intel 8051: Power On Reset RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles The oscillator start-up time depend on the oscillator frequency Port pins will be in a random state until the oscillator has started and the internal reset algorithm has written 1s to them Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location

69. Intel 8051: EPROM Versions Electrically programmable by user Relative slow Limited number of erase/write cycles

70. Intel 8051: OTP Versions One Time Programmable It is standard EPROM without erasing window It is used for limited production

71. Intel 8051: FLASH Versions Supports in-system and in-board code changes Electrically erasable Reduces code inventory and scrap Simplifies the task of upgrading code and reduces upgrade cycle time Provides just-in-time system software downloads Truly non-volatile

72. Intel 8051: The On-Chip Oscillator Intel 8051 microcontrollers have an on-chip oscillator resonators are connected between XTAL1 and XTAL2 pins external oscillators (HMOS or CMOS)

73. Intel 8051: Power Management Low power devices Power saving Voltage monitoring

74. Intel 8051: Power Reduction Modes CHMOS versions provides power reduced modes of operations There are two power reducing modes Idle and Power Down In the Idle mode oscillator continues to ran Interrupt, Timer and Serial Port blocks continue to be clocked clock signal is gated off to the CPU In the Power Down mode the oscillator is frozen

75. Intel 8051: Instruction Set

76. Intel 8051: Instruction Set

77. Intel 8051: Instruction Set

78. Intel 8051: Instruction Set

79. Intel 8051: Instruction Set

80. Intel 8051: Instruction Set

81. Intel 8051: Instruction Set

82. Intel 8051: Instruction Set

83. Intel 8051: Addressing Modes Immediate Addressing Direct Addressing Indirect Addressing refers to Internal RAM, never to an SFR External Direct only two commands that use External Direct DPTR holds the correct external memory address External Indirect Code Indirect MOV A,#20h MOV A,30h MOV A,@R0 MOVX A,@DPTR MOVX @DPTR,A MOVX @R0,A MOVC A,@A+DPTR

84. Worldwide Microcontroller shipments - in millions of dollars -

85. Intel 8051: Manufacturers AMD ARM Microcontrollers ARC Cores Atmel Dallas Hitachi semiconductors Intel ISSI Matra Microchip OKI Philips Siemens SMC SSI Texas Instruments ZiLog etc.

86. Intel 8051: Additional Features Watch Dog Timers Clock Monitor Resident Program Loader Software protection ?P Supervisory Circuit

87. Watch Dog Timers Provides a means of graceful recovery from a system problem If the program fails to reset the watchdog at some predetermined interval, a hardware reset will be initiated Especially useful for unattended systems

88. Clock Monitor If the input clock is too slow, a clock monitor can shut the microcontroller down Usually software controlled status (on/off)

89. Resident Program Loader Loads a program by initializing program/data memory from either a serial or parallel port Eliminates the erase/burn/program cycle (typical with EPROM’s) Allows system updating from an offsite location

90. Software protection Protect unauthorized snooping (reverse engineering, modifications, piracy, etc. Only OTPs and Windowed devices option

91. ?P Supervisory Circuit Functions: ?P reset (active low or high) Manual reset input Two stage power fall warning Backup-battery switchover Write protection of RAM 2.275 threshold detector Battery OK flag indicator Watch Dog timer

92. ?P Supervisory Circuit

93. ?P Supervisory Circuit

94. ?P Supervisory Circuit

95. Characteristics Comparisons

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