Elen 468 advanced logic design
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ELEN 468 Advanced Logic Design. Lecture 7 System Tasks, Functions, Syntax and Behavioral Modeling I. System Tasks and Functions. Display Tasks. $monitor $monitor (“%d %f %b %b”, $time , $realtime , x, y); Continuously display values $display , $displayb , $displayo , $displayh

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ELEN 468 Advanced Logic Design

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Elen 468 advanced logic design

ELEN 468Advanced Logic Design

Lecture 7

System Tasks, Functions, Syntax

and Behavioral Modeling I

ELEN 468 Lecture 7


System tasks and functions

System Tasks and Functions

ELEN 468 Lecture 7


Display tasks

Display Tasks

  • $monitor

    • $monitor(“%d %f %b %b”, $time, $realtime, x, y);

    • Continuously display values

  • $display, $displayb, $displayo, $displayh

    • $display(“x = %b y = %b”, x, y);

    • Display once only

  • $write, $writeb, $writeo, $writeh

    • $write(“x = %b y = %b”, x, y);

    • Same as display, but no “\n”

ELEN 468 Lecture 7


Files

$fopen, $fclose, $fdisplay

module test_bench();

reg x;

wire y;

integer cd;

assign y = ~x;

initial begin

cd = $fopen("test.dat");

#100 x = 0;

$fdisplay(cd, "%b %b", x, y);

$fclose(cd);

end

endmodule

Files

channel descriptor

ELEN 468 Lecture 7


Read memory

Read Memory

parameter ram_file = “ram_data_file”;

reg [15:0] RAM_1 [0:1023];

initial

$readmemh(ram_file, RAM_1);

// read input file as hexadecimal

initial

$readmemb(ram_file, RAM_1);

// read input file as binary

ELEN 468 Lecture 7


Simulation control

Simulation Control

initial

#200 $finish;

  • $finish and $finish(n)

    • n = 0, print nothing

    • n = 1, print simulation time and location

    • n = 2, print simulation time, location and statistics

  • $stop(n): interactive mode

initial begin

#20 x=0; y=0;

$stop(0);

ELEN 468 Lecture 7


Probability distribution

range

mean

standard deviation

Probability Distribution

Generate different types of distributions

integer seed, d;

d = $dist_uniform(seed, 0, 9);

d = $dist_exponential(seed, 3);

d = $dist_normal(seed, 0, 5);

ELEN 468 Lecture 7


Compiler directives

`timescale

`include

`defaultnettype

`define and `undef

`ifdef, `else, `endif

`include “testbench.v”

`defaultnettypewor

`define wait_state 3’b010

`undef wait_state

`ifdef BEHAVIORAL

y = x1 | x2;

`else

or ( y, x1, x2 );

`endif

Compiler Directives

ELEN 468 Lecture 7


Syntax

Syntax

ELEN 468 Lecture 7


Bnf formal syntax notation

BNF Formal Syntax Notation

  • BNF = Backus-Naur Form or Backus Normal Form

  • ::= definition of syntax

  • | alternative syntax

  • […] appear once or not at all

  • {…} appear any times, or not at all

ELEN 468 Lecture 7


Example of verilog syntax

Example of Verilog Syntax

source_text ::= { description }

description ::= module_declaration

| udp_declaration

module_declaration ::=

module_keyword module_identifier

[list_of_ports];

{ module_item }

endmodule

module_keyword ::=

module | macromodule

ELEN 468 Lecture 7


Elen 468 advanced logic design 1345351

list_of_ports ::= ( port {, port} )

module_item ::=

module_item_declaration

| parameter_overwrite

| continuous_assign

| gate_instantiation

| udp_instantiation

| module_instantiation

| specify_block

| initial_construct

| always_construct

ELEN 468 Lecture 7


Elen 468 advanced logic design 1345351

continuous_assign ::= assign [drive_strength]

[delay3] list_of_net_assignments;

drive_strength ::= ( strength0, strength1)

delay3 ::= #delay_value

| #(delay_value [, delay_value [, delay_value]] )

list_of_net_assignments ::= net_assignment

{, net_assignment }

net_assignment ::= net1_value = expression

ELEN 468 Lecture 7


Elen 468 advanced logic design 1345351

Behavioral Modeling I

ELEN 468 Lecture 7


Structural vs behavioral descriptions

Structural vs. Behavioral Descriptions

module my_module(…);

assign …; // continuous assignment

and (…); // instantiation of primitive

adder_16 M(…); // instantiation of module

always @(…)

begin … end

initial

begin … end

endmodule

Structural, no order

Behavior, in order in each procedure

ELEN 468 Lecture 7


Behavioral descriptions in general

Behavioral

Procedural

Behavioral Descriptions In General

  • Co-exists with gate instantiations

  • Not all descriptions synthesize

  • Not all synthesized descriptions are desirable

  • Non-structural behaviors

    • Continuous assignment

    • initial

    • always

  • Within a module

    • Multiple behaviors are allowed

    • Nested behaviors are not allowed

ELEN 468 Lecture 7


Behavioral statements

initial | always

single_statement; |

begin

block_of_statements;

end

initial

Activated from tsim = 0

Executed once

Initialize a simulation

always

Activated from tsim = 0

Executed cyclically

Continue till simulation terminates

Behavioral Statements

ELEN 468 Lecture 7


Example of behavioral statement

Example of Behavioral Statement

module clock1 ( clk );

parameter half_cycle = 50;

parameter max_time = 1000;

output clk;

reg clk;

initial

clk = 0;

always

begin

#half_cycle clk = ~clk;

end

initial

#max_time $finish;

endmodule

clk

50

100

150

200

tsim

ELEN 468 Lecture 7


Assignment

Assignment

  • Continuous assignment

    • Values are assigned to net variables due to some input variable changes

    • “assign …=… “

  • Procedural assignment

    • Values are assigned to register variables when certain statement is executed in a behavior

    • Procedural assignment, “=“

    • Procedural continuous assignment, “assign …=… [deassign] “

    • Non-blocking assignment, “<=“

ELEN 468 Lecture 7


Blocking and non blocking assignment

initial

begin

a = 1;

b = 0;

a = b; // a = 0;

b = a; // b = 0;

end

initial

begin

a = 1;

b = 0;

a <= b; // a = 0;

b <= a; // b = 1;

end

Blocking assignment “=“

Statement order matters

A statement has to be executed before next statement

Non-blocking assignment “<=“

Concurrent assignment

If there are multiple non-blocking assignments to same variable in same behavior, latter overwrites previous

Blocking and Non-blocking Assignment

ELEN 468 Lecture 7


Procedural continuous assignment

Procedural Continuous Assignment

  • Continuous assignment establishes static binding for net variables

  • Procedural continuous assignment (PCA) establishes dynamic binding for variables

    • “assign … deassign” for register variables only

    • “force … release” for both register and net variables

ELEN 468 Lecture 7


Assign deassign pca

Binding takes effect when PCA statement is executed

Can be overridden by another PCA statement

“deassign” is optional

“assign” takes control, “deassign” release control

PCA overwrites procedural assignments

module flop ( q, qbar, preset,

clear, clock, data );

assign qbar = ~q;

initial

q = 0;

always @ ( negedge clk )

q = data;

always @ ( clear or preset )

begin

if ( !preset ) assign q = 1;

else if ( !clear ) assign q = 0;

elsedeassign q;

end

endmodule

“assign … deassign” PCA

ELEN 468 Lecture 7


Example of assign

Example of assign

module mux4_PCA(a, b, c, d, select, y_out);

input a, b, c, d; input [1:0] select;

output y_out; reg y_out;

always @(select)

begin

if (select == 0) assign y_out=a;

else if (select == 1) assign y_out=b;

else if (select == 2) assign y_out=c;

else if (select == 3) assign y_out=d;

elseassign y_out=1’bx;

end

endmodule

y_out changes with a;

ELEN 468 Lecture 7


Alternative

Alternative

module mux4_PCA(a, b, c, d, select, y_out);

input a, b, c, d; input [1:0] select;

output y_out; reg y_out;

always @(select or a or b or c or d)

begin

if (select == 0) y_out=a;

else if (select == 1) y_out=b;

else if (select == 2) y_out=c;

else if (select == 3) y_out=d;

else y_out=1’bx;

end

endmodule

Value of ‘a’ is assigned to y_out at this time

ELEN 468 Lecture 7


Force release pca

force sig1 = 0;

force sig2 = 1;

Sig3 = 0;

#9 sig3 = 1;

release sig1;

release sig2;

Similar to “assign…deassign”

Can be applied to net variables

Often applied in testing

modA

sig1

sig2

modB

sig3

“force … release” PCA

ELEN 468 Lecture 7


Comparisons of assignment

Comparisons of Assignment

ELEN 468 Lecture 7


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