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Implementation of Silicon Track Card (STC) as a System-On-a-Programmable-Chip (SOPC)

Implementation of Silicon Track Card (STC) as a System-On-a-Programmable-Chip (SOPC). Presentation by Arvindh Lalam and Dr. Reginald Perry Department of Electrical and Computer Engineering Florida A&M University – Florida State University College of Engineering. IEEE SoutheastCon 2002

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Implementation of Silicon Track Card (STC) as a System-On-a-Programmable-Chip (SOPC)

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  1. Implementation of Silicon Track Card (STC) as a System-On-a-Programmable-Chip (SOPC) Presentation by Arvindh Lalam and Dr. Reginald Perry Department of Electrical and Computer Engineering Florida A&M University – Florida State University College of Engineering IEEE SoutheastCon 2002 SEC 143

  2. ExampleSilicon Track Card (STC) for the DZERO Experiment: Overview • The DZERO Experiment is conducted at Fermi National Acceleration Laboratory. • In the D0 experiment a proton – anti protonare made to collide after high acceleration in the TeVatron accelerator. The TeVatron Accelerator Physicists examine the results from the collisions in an attempt to understand the fundamental nature of matter.

  3. Example:Problem Statement Each “experiment” generates billions of collisions. How do you only collect data from collisions of “interest.” Dzero Detector http://www.fnal.gov

  4. Example :Conceptualization road data CFT Fiber Road Card Few ms Time Budget SMT data Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card DZERO Track Fit Card L2

  5. Trigger Detector Level 1 Level2 SMT L2 Cal L1 CAL L2 Ps preprocess SMT data L1 CFT find clusters CAL L2 Global Level 3 L2 CFT associate clusters with L1CTT tracks L1CTT L2 STT FPS/ CPS fit trajectories L1 Muon L2 Muon L1 FPD L2CTT CFT L1 Framework SMT Muon FPD D0 Trigger

  6. STC L1CTT SMT FRC preprocess SMT data find clusters L3 associate clusters with L1CTT tracks fit trajectories TFC L2CTT The Level_2 STT

  7. CFT H Layer 2 mm road hits CFT A Layer centroids SMT Layers “Si” strips D0 Trigger - STC • “road” : Track information translated for the STC. • “clusters” : Groups of strips. • “centroid”: Centroid of a cluster. • “hit” : A centroid that falls in a road.

  8. STC - Functionality • Reformats received “strip” data. • Finds “Clusters” and their “centroids”. • Identifies “hits”. • Stores required data for debugging. • Implements a Bus Arbitration scheme. • Operates at 33 MHz.

  9. SMT Data Data from the main controller Strip Reader Downloaded Parameters Centroid Finder L3 FiFos To L3 Hit Filter Control Lines Roads from FRC Handshake Signals Hits Control Lines Main Control Data Lines STC - Main Data Path

  10. Centroid Finder Algorithm =cluster center

  11. 22..21 16..15 20 14..13 19 12..2 18..11 1..0 10..7 6..0 Data type Data type New data bit Pulse Area End of data Centriod Data Precision bits Chip Id Strip number Data from memory F I F O To Hit filter From Strip reader Cluster Finder Centroid Calculator To Hit filter To L3 Buffer Example Centroid Finder 23 17 From Strip Reader: Data Streams To Hit Filter:

  12. VHDL Code entity cluster_finder is port( data_in: in unsigned(22 downto 0); -- input data word from fifo data_threshold_1,data_threshold_2: in unsigned(7 downto 0); -- read as inputs cluster_type: in unsigned(0 downto 0); -- use 3 or 5 strips in scalculation 800+ lines later end behavior;

  13. Programmable Logic Devices (FPLDs) • Re-programmable Logic devices. • Eg: CPLDs, FPGAs, FPLDS Altera FLEX 10KE • Fast Prototyping, Fast turnaround time. • STC previously used CPLDs.

  14. System-On-a-Programmable-Chip (SOPC) • Discrete PCB components? • SOPC • Altera APEX II EP2A90 7M gates: 1.5Mbits SRAM • Xylinx Virtex E XC2V10000 10M gates: 3.4 Mbits SRAM • Altera APEX 20KE • EP20K600EBC652-1X • Accommodates 1 STC

  15. STC - Prototype Testing Board • Control Logic • BU • Silicon Track Card • FAMU-FSU COE

  16. STC Waveforms - Hit readout • Write Signals • ‘HR_WR0’ & ‘HR_WR1’ • Contains header & footer • STC0 : 7 hits • STC1 : 2 hits

  17. STC - Resources

  18. Conclusions • STC functionality successfully tested. • Circuit operational at 33 MHz. • Contention scheme for multiple channels successfully tested. • Successfully integrated STC in a SOPC.

  19. Acknowledgements • National Science Foundation and the US Department of Energy. • Boston University • Faculty: Heintz, Narain, Popkov • Engineers: Earle, Hazen • Students: Zabi • Florida State University – Physics • Faculty: Adams, Prosper, Wahl • Postdocs: Tentindo-Repond • Florida A&M University – Florida State University COE • Faculty: Perry • Students: Lalam, Lolage, Meyers, Roper, Saunders • Altera, Aldec, Synopsys

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