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A Scalable Architecture for Multiplier over Finite Fields GF (2 m )

A Scalable Architecture for Multiplier over Finite Fields GF (2 m ). *Kwang-Jin Lee, *Yong-Hee Jang , *Yong-Jin Kwon. Dept. Telecommunication and Information Eng. Hankuk Aviation University. Logic Circuit Lab. Hankuk Aviation Univ. Overview. Introduction

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A Scalable Architecture for Multiplier over Finite Fields GF (2 m )

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  1. A Scalable Architecture for Multiplier over Finite Fields GF(2m) *Kwang-Jin Lee, *Yong-Hee Jang , *Yong-Jin Kwon Dept. Telecommunication and Information Eng. Hankuk Aviation University Logic Circuit Lab. Hankuk Aviation Univ.

  2. Overview • Introduction • Importance of multiplication over GF(2m) • Problem on current multipliers over GF(2m) • Scalable architecture • Multiplication Algorithm over GF(2m) for Scalable Architecture • Scalable Architecture for Multiplier over GF(2m) • Structure of PE(Processing Element) • Pipeline organization • Memory organization • Evaluation and Analysis of the proposed architecture for multiplier • Analysis of execution time by hardware configuration • Comparison of the execution time • Conclusion Logic Circuit Lab. Hankuk Aviation Univ.

  3. Introduction (Continue) • Finite Fields are used in various applications : cryptography, digital signal processing and error correcting code • Importance of multiplication over GF(2m) • Operations over GF(2m) : addition, subtraction, multiplication and multiplicative inversion • Multiplication has the highest time and area complexities Logic Circuit Lab. Hankuk Aviation Univ.

  4. Introduction (Continue) • Problem of current multipliers over GF(2m) • Bit by parallel • To reduce time complexity • Bit-Serial by parallel • To reduce area complexity • Multiplier has to be redesigned when input precision is increased Logic Circuit Lab. Hankuk Aviation Univ.

  5. Introduction • Scalable Architecture • The architecture which performs operations regardless of input precision • Originally designed arithmetic unit can be reused or replicated in order to generate long precision result • Without change the data path precision for the arithmetic unit • Easily used for various systems Logic Circuit Lab. Hankuk Aviation Univ.

  6. Multiplication Algorithm over GF(2m) for Scalable Architecture • MSB-First multiplication method • Bit-Serial by word multiplication method • XOR, AND, shift operation without modular operation 1≤ i≤ m-1 i=0 Logic Circuit Lab. Hankuk Aviation Univ.

  7. Scalable Architecture for Multiplier over GF(2m) • Consists of PE, FF, Memory, Register-A and Control Block • Every data path has the width of w-bit expect ai Logic Circuit Lab. Hankuk Aviation Univ.

  8. Structure of PE • PE is designed to perform repeated function in the algorithm • Consists of AND, XOR, FF, ALIGNMENT, MUX Logic Circuit Lab. Hankuk Aviation Univ.

  9. Memory Organization • RAM A, B and P perform reading only • RAM C performs both reading and writing • Perform both reading and writing on different addresses at a time • Eliminate delaying factors Logic Circuit Lab. Hankuk Aviation Univ.

  10. Pipeline Organization • The property of the algorithm is that it performs the same function repeatedly • PE is designed to perform repeated function in this algorithm • The output of PE in step-(j) depends on the output of PE in step-(j+1) Logic Circuit Lab. Hankuk Aviation Univ.

  11. Simulation Result of The Proposed Architecture • The result of timing simulation • Simulation vectors A(x) = x3 + x2 + x + 1 B(x) = x3 + x2 + x P(x) = x4 + x + 1 C(x) = x2 + 1 Logic Circuit Lab. Hankuk Aviation Univ.

  12. Evaluation and Analysis of the Proposed Architecture for Multiplier (Continue) • Execution time T = tcycle · period • Clock cycles tcycle = tinit + (tloop· ttotle-PE) + tDPRAM - tR Logic Circuit Lab. Hankuk Aviation Univ.

  13. Evaluation and Analysis of the Proposed Architecture for Multiplier (Continue) • Clock period according to word length obtained by analysis of P&R(Post-place &Route) Logic Circuit Lab. Hankuk Aviation Univ.

  14. Evaluation and Analysis of the Proposed Architecture for Multiplier (Continue) • Execution time by the number of PEs and word length (k, w) = (10, 32), (20, 16), (40, 8) Logic Circuit Lab. Hankuk Aviation Univ.

  15. Evaluation and Analysis of the Proposed Architecture for Multiplier • Comparison of the execution time between multiplier[4] and proposed multiplier (k=4, w=4) Logic Circuit Lab. Hankuk Aviation Univ.

  16. Conclusion • We proposed a scalable architecture for multiplier over GF(2m) which does not need to be redesigned when the precision is increased • MSB-First multiplication method • Bit-serial by word multiplication method • Less execution time compare to the current system in other paper • Easily used for various systems Logic Circuit Lab. Hankuk Aviation Univ.

  17. Thank You! Logic Circuit Lab. Hankuk Aviation Univ.

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