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VLSI Memory Design

VLSI Memory Design. Shmuel Wimer Bar Ilan University, School of Engineering. A memory has 2 n words of 2 m bits each. Usually 2 n >> 2 m , (e.g. 1M Vs. 64) which will result a very tall structure.

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VLSI Memory Design

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  1. VLSI Memory Design Shmuel Wimer Bar Ilan University, School of Engineering

  2. A memory has 2n words of 2m bits each. Usually 2n >> 2m, (e.g. 1M Vs. 64) which will result a very tall structure. The array is therefore folded into 2n-k rows, each containing 2k words, namely, every row contains 2m+k bits. Consider 8-words of 4-bit memory. We’d like to organize it in 4 lines and 8 columns. The memory is folded into 4-word by 8-bit, so n=3, m=2 and k=1. Larger memories are built from smaller sub-arrays to maintain short word and bit lines.

  3. Bit-line Conditioning Word-lines Bit-lines Array of 2nx2m cells, organized in 2n-k rows by 2m+k columns Row Decoder n-k k Column Circuitry n Column Decoder 2m bits General Memory architecture 8-word by 4-bit folded memory

  4. bit 12-Transistor SRAM Cell When write=1 the value at the bit is passed to the middle inverter while the upper tri-state inverter is in high Z. Once write=0 the upper and the center inverters are connected in a positive feedback loop to retain cell’s value as long as write=0. The value of bit-line needs to override the value stored at the cell. It requires careful design of transistor size for proper operation.

  5. bit 12-Transistor SRAM Cell When read=1 the output of the lower tri-state inverter gets connected to the bit so cell’s value appears on the bit-line. The bit-line is first pre-charged to one, so only if the value stored at cell is zero the bit-line is pulled down.

  6. Though robust, 12-transistor cell consumes large area. Since it dominates the SRAM area, a 6-transistor is proposed, where some of the expense is charged on the peripheral circuits. 6-Transistor SRAM Cell

  7. Lithography simulation Layout design Silicon Layout of IBM 0.18u SRAM cell

  8. P2 P1 N2 N4 N1 N3 Read Write Operations SRAM operation is divided into two phases called Φ1 and Φ2, which can be obtained by clk and its complement. Pre-charge both bit-lines high. Turn on word-line. One of the bit-lines must be pulled-down. Since bit-line was high, the 0 node will go positive for a short time, but must not go too high to avoid cell switch. This is called read stability.

  9. Read Stability A must remain below threshold, otherwise cell may flip. Therefore N1>>N2.

  10. P2 P1 Weak N2 N4 Medium N1 N3 Strong Let A=0 and assume that we write 1 into cell. In that case bit is pre-charged high and its complement should be pulled down. It follows from read stability that N1>>N2 hence A=1 cannot be enforced through N2. Hence A complement must be enforced through N4, implying N4>>P2. This constraint is called writability.

  11. Writability

  12. Bit-line Conditioning Φ1 Φ2 word bit SRAM Cell H H Bit-lines are precharged high SRAM Column Read Operation For delay reduction outputs can be sensed by high-skew inverters (low noise margin).

  13. Bit-line Conditioning SRAM Cell write data Write Driver SRAM Column Write Operation Bit-lines (and complements) are precharged high. At write one is pulled down. Write operation overrides one of the pMOS transistors of the loop inverters. Therefore, the series resistance of transistors in write driver must be low enough to overpower the pMOS transistors.

  14. A3 A2 A0 A1 common factor word1 word0 word15 Decoders To decode word-lines we need AND gates of n-k inputs. This is a problem when fan-in of more than 4 since it slows down decoding. It is possible to break the AND gates into few levels as shown in the 4:16 decoder.

  15. A3 A2 A0 A1 word15 word0 word1 Pre-coded Lines Terms repeats themselves, so pre-decoding will eliminate the redundant ones. This is called pre-decoding. Less area with same drive as before.

  16. Vcc 2x x 1 1 word0 x 1 1 word1 x 2x 1 1 word2 x 1 1 word3 Lyon-Schediwy Fast Decoders In a NOR implementation output is pulled up via serial pMOS devices, which slows transition, so pMOS needs sizing, but this consumes lot of area. Since only single word is pulled up at a time, pMOS can be shared between words in a binary tree fashion and sized to yield same current as in pull down.

  17. Sum-addressed Decoders Sometimes an address of memory is calculated as BASE+OFFSET (e.g., in a cache), which requires an addition before decoding. Addition can be time consuming if Ripple Carry Adder (RCA) is used, and even Carry Look Ahead (CLA) my be too slow. It is possible to use a K = A + B comparator without carry propagation or look-ahead calculation.

  18. Sum-addressed Decoders If we know A and B, we can deduce what must be the carry in of every bit if it would happen that K = A + B . But then we can also deduce what should be the carry out. It follows that if every bit pair agrees on the carry out of the previous with the carry in of the next, then K=A+B is true indeed. Consequently, we can use a comparator to every word-line, where equality will hold only for one word.

  19. We can derive the equations of the carries from the required and generated carries below.

  20. Below is a comparison of sum-addressed decoder with ordinary decoder combined with a ripple carry adder (RCA) and carry look ahead adder (CLA). A significant delay and area improvement is achieved.

  21. Used to precharge bits high before R/W operation. Most simple is the following circuit. If a clock is not available it is possible to use a weak pMOS device connected as a pseudo-nMOS SRAM. Precharge can be done with nMOS, a case where precharge voltage is Vdd-Vt. It results faster R/W since swing is smaller, but noise margin is worsen. Bit-Line Conditioning Circuits

  22. This is a differential analog pair. N3 is a current source where current flows either in left or right branches. Circuit doesn’t need a clock but it consumes significant amount of DC power. P2 P1 N2 N1 N3 Sense Amplifiers Each column contains write driver and read sensing circuit. A high skew read inverter has been shown. Sense amplifier provides faster sensing by responding to a smaller voltage swing.

  23. Isolation Devices Regenerative Feedback To speed up response bit-lines are disconnected at sensing to avoid their high capacitive load. The regenerative feedback loop is now isolated. When sense clock is high the values stored in bit-lines are regenerated, while the lines are disconnected, speeding up response.

  24. Isolation Devices Regenerative Feedback Sense amplifiers are susceptible to differential noise on bit-lines since they respond to small voltage differences.

  25. Column Multiplexers The SRAM is physically organized by 2n-k rows and 2m+k columns. Each row has 2m groups of 2k bits. Therefore, a 2k:1 column multiplexers are required to extract the appropriate 2m bits from the 2m+k ones.

  26. To sense Amps and Write Circuits Tree Decoder Column Multiplexer The problem of this MUX is the delay occurring by the series of pass transistors.

  27. A1 A0 B0 B0 B1 B1 B2 B3 Y It is possible to implement the multiplexer such that data is passed trough a single transistor, while column decoding takes place concurrently with row decoding, thus not affecting delay.

  28. DRAM – Dynamic RAM • Store their charge on a capacitor rather than in a feedback loop • Basic cell is substantially smaller than SRAM. • To avoid charge leakage it must be periodically read and refresh • It is built in a special process technology optimized for density • Offers order of magnitude higher density than SRAM but has much higher latency than SRAM

  29. bit A 1-transistor (1T) DRAM cell consists of a transistor and a capacitor. Cell is accessed by asserting the word-line to connect the capacitor to the bit-line. word x Ccell On a read the bit-line is first precharged to VDD/2. When the word-line rises, the capacitor shares its charge with the bit-line, causing a voltage change of ΔV that can be sensed. word The read disturbs the cell contents at x, so the cell must be re-written after each read. x bit On a write the voltage of the bit-line is forced onto the capacitor

  30. DRAM Cell Ccell must be small to obtain high density, but big enough to obtain voltage swing at read.

  31. bit0 bit1 bit511 word0 word1 word255 Like SRAMs, large DRAMs are divided into sub-arrays, whose size represents a tradeoff between area and performance. Large sub-arrays amortize sense amplifiers and decoders among more cells but are slower and have less swing due to higher capacitance of word and bit lines. Bit-line capacitance is far larger than cell, hence voltage swing ΔV during read is very small and sense amplifier is used.

  32. Open bit-line architecture Is useful for small DRAMs. It has dense layout but sense amps are exposed to differential noise since their inputs come from different sub-arrays, while word line is asserted in one array. Folded bit-line architecture solves the problem of differential noise on the account of area expansion. Sense amps input are connected to adjacent bit-lines exposed to similar noise sources. When a word-line is asserted, one bit line is being read while its neighbor serves as the quiet reference. Smart layout and aggressive manufacturing design rules (e.g. 45 degrees polygons) enable effective area increase of only 33%.

  33. Sub-array 1 Word-Line Decoders Word-Line Decoders Sense Amps Word-Line Decoders Word-Line Decoders Sub-array 2 Open Bit-Line Architecture

  34. Sense Amps Word-Line Decoders Word-Line Decoders Sense Amps Folded Bit-Line Architecture

  35. Polysilicon Word-Line Metal Bit-Line Word-Line Decoder Word-Line Decoder Word-Line Decoder Word-Line Decoder n+ Diffusion Bit-Line Contact Capacitor Sense Amp Sense Amp

  36. Vp P2 P1 N1 N2 Vn bit’ bit” DRAM Sense Amp bit’ and bit” are initialized to VDD/2. Vp=0 and Vn= VDD/2, so all transistors are initially OFF. During read one bit-line is changing while the other stays float in VDD/2. Let bit’ change to 0. Once it reaches VDD/2-Vt, N1 conducts and it follows bit’. Hence Vn is pulled down. Meanwhile bit” is pulled up, which opens P2 and raise Vp to VDD.

  37. VDD Bit” VDD/2 Bit’ 0 VDD VDD/2 Vn Vp 0

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