A 2.7mW linear-in-dB VGA with 60dB tuning range and two DC offset cancellation loops

1. Radio-Frequency Integration Technology – RFIT 2005 A 2.7mW linear-in-dB VGA with 60dB tuning range and two DC offset cancellation loops Chien M. Ta Chee Hong Yong Wooi Gan Yeoh Nov. 30 – Dec. 2, 2005 Institute of Microelectronics

2. Outline • Introduction • Specifications • Circuit description • Measurement results • Concluding remarks and future works • Acknowledgement

3. Introduction Motivation • A Direct Conversion Receiver for Ultra-Wideband communications Objective • A low-power Variable Gain Amplifier with DC Offset Cancellation mechanism

4. Specifications

5. LPF LPF Variable-gain Variable-gain Fixed-gain _ _ OUT IN + + Adder Adder V-to-I converter Control voltage Architecture Two DC offset cancellation loops at the input and the output of the VGA to suppress DC offset in the input signal and DC offset caused by mismatches in the circuit itself.

6. LPF Fixed-gain _ + Adder DC offset cancellation Output DC offset is extracted and negatively fed back to cancel the DC offset at the input of the fixed gain block.

7. OUT1 OUT2 IN1 IN2 Is Is Fixed-gain stage • Differential pair with degenerative resistor: simple, stable, and linear • Split tail current: save voltage headroom • Issues: matching between the components (solved by interdigitizing)

8. OUT1 OUT2 IN2 IN1 IN1 Is1 Is1 Is2 Is2 Vc Is2 Is1 Variable-gain stage • Gilbert cell with degenerative resistors: large gain range (30dB linear-in-dB gain range) • Split tail current: save voltage headroom • Issues: matching between the components (solved by interdigitizing) V-to-I converter

9. Gain tuning curve • Gain can be tuned linear-in-dB from -3dB to 57dB (the specification is from 0dB to 60dB) when the control voltage is varied from 0.2V to 0.9V

10. Frequency response • Low cutoff frequency at 600kHz (specification is <500kHz) • 3-dB bandwidth of 130MHz (specification is >100MHz)

11. DC offset cancellation • Output DC offset is below 20mV for input DC offset up to 40mV and below 10mV for input DC offset up to 10mV

12. Summary of the design

13. Concluding remarks and Future works What have been achieved? • A functional VGA architecture with two DC offset cancellation loops • Tunable gain in dB-linear fashion with respect to the control voltage • Maximum gain is as high as 57dB • Satisfactory bandwidth of 130MHz • Very low power consumption, 2.7mW • Very small die area, 243μm x 264μm (0.064mm2) What to do next? • Improve the linearity by redesigning the last stage of the VGA; more power consumption is needed • Improve noise performance of the VGA by carefully redesigning the first stage • Reduce mismatch in the layout to get better DC offset cancellation

14. Acknowledgement • Dr. Lin Fujiang for coordinating the project • Dr. Zheng Yuanjin, Mr. Ben Choi, Mr. Teo Tee Hui, and Mr. Wong Sheng Jau for their advice during the design • Ms. Wu Ye and Mr. Ram Chandra Yadav for reviewing the paper • IME management

15. THANK YOU

16. Benchmarking