Automated Generation of the Register Set of a SOC and its Verification Environment

1. 18th Panhellenic Conference on Informatics Automated Generation of the Register Set of a SOC and its Verification Environment K. Poulos, K. Adaos, G.P. Alexiou Dept. of Computer Engineering and Informatics Univ. of Patras, Greece

2. Agenda • Introduction • System Environment • UVM Register Layer • Register Field Template • Register File Template • Register Generation Procedure • Examples • Conclusion – Current Work Dept. of Computer Engineering and Informatics, Univ. of Patras

3. Introduction • Part of System-on-Chip Platform for Research and Education • Result of a graduate thesis in the VLSI Lab of CEID. • Target: Develop an automated tool that • Generates the synthesizabe set of the registers of a SOC • Generates its verification environment • Be compliant with design and verification standards Dept. of Computer Engineering and Informatics, Univ. of Patras

4. System Environment • The register file enables the parts of the system to communicate and control each other. Dept. of Computer Engineering and Informatics, Univ. of Patras

5. System Environment • The register file enables the parts of the system to communicate and control each other. • A processor or a HOST system can change the behavior of the SOC Dept. of Computer Engineering and Informatics, Univ. of Patras

6. System Environment • The register file enables the parts of the system to communicate and control each other. • A processor or a HOST system can change the behavior of the SOC • Peripherals return data and status Dept. of Computer Engineering and Informatics, Univ. of Patras

7. UVM Register Layer • UVM is the industry standard for verification • Object Oriented , Based on SystemVerilog • Provides a set of predefined agents to control and monitor the bahavior of the DUV • Constraint Randomization Techniques Dept. of Computer Engineering and Informatics, Univ. of Patras

8. UVM Register Layer • UVM Register Layer is a part of the UVM spec • Models the behavior of the registers of a SOC/HW design based on their properties • Enables frontdoor/backdoor access to the registers during verification • With predefined operations, the user can bypass/omit HW components and focus on the peripheral operation • Our tool supports registers named after the UVM register layer => Consistent view of design and verification process. Dept. of Computer Engineering and Informatics, Univ. of Patras

9. Register Field Template • A generic register template is utilized with an interface that is common in all fields • Two access ports: • Bus Port (activated during bus operations) • HW Port (driven by a HW module/state machine). • Differentiation is done internally based on the register’s properties Dept. of Computer Engineering and Informatics, Univ. of Patras

10. Register Field Template • Differentiation is done internally based on the properties of the processor port Dept. of Computer Engineering and Informatics, Univ. of Patras

11. Register Field Template • RO : A read only register can be written by HW blocks (via signals hw_we and hw_din) and can only be read by the Bus of the System (via ports bus_re and bus_dout) Dept. of Computer Engineering and Informatics, Univ. of Patras

12. Register Field Template • Other register field types model other common HW operations: • W1C: To clear the register, the processor has to write logic-1 (for example for clearing an interrupt flag). Dept. of Computer Engineering and Informatics, Univ. of Patras

13. Register Field Template • RW : A Read/Write field uses all ports Dept. of Computer Engineering and Informatics, Univ. of Patras

14. Register Field Code example Dept. of Computer Engineering and Informatics, Univ. of Patras

15. AHB Register File Architecture • A register consists of one or more register fields. • The AHB bus interface logic adapts the AHB bus signals to the bus access signals (bus_we, bus_re, bus_din, bus_dout). • By changing only the bus interface logic we can support bus standards different than the AHB. Dept. of Computer Engineering and Informatics, Univ. of Patras

16. Register File Generation • Generation is based on three input files • Register File Desciption(the only file defined by the user) • A predesigned Register Field Template • A predesigned Register File Template Dept. of Computer Engineering and Informatics, Univ. of Patras

17. Register File Generation • The generator provides three outputs • A synthesizable system verilog file with the register file description • A C header file (compatible with GNU compilers) • The description of the register file according to UVM register layer to be used for verification Dept. of Computer Engineering and Informatics, Univ. of Patras

18. Register File Description File • Name • Position - Width • Address • Type • Reset Value • Comment (optional) Dept. of Computer Engineering and Informatics, Univ. of Patras

19. Register File Description File • Text Based: Easily Integrates in a Version Control System (we use git) • Available parsers can also support spreadsheet files (Microsoft xls or OpenOffice) Dept. of Computer Engineering and Informatics, Univ. of Patras

20. Example Simple microcontroller (175 total register bits) Dept. of Computer Engineering and Informatics, Univ. of Patras

21. Example Simple microcontroller (175 total register bits) Dept. of Computer Engineering and Informatics, Univ. of Patras

22. Example Simple microcontroller (175 total register bits) Dept. of Computer Engineering and Informatics, Univ. of Patras

23. Current Work • Support of extra register fields and types • Support of additional bus standards(Wishbone, APB, AXI) • GUI support • Extend automation in other SOC components Dept. of Computer Engineering and Informatics, Univ. of Patras

24. Automated Generation of the Register Set of a SOC and its Verification Environment adaos@ceid.upatras.gr www.ceid.upatras.gr/webpages/faculty/alexiou/vlsilab Dept. of Computer Engineering and Informatics, Univ. of Patras