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STT-RAM Generator. - Anurag Nigam. Challenges in SRAM High Leakage Solution Non-volatile memory. Leakage current. Motivation. Memory Technology Comparison. Hard Ferro magnetic layer. BL. Oxide layer. MTJ. R P. Free Ferro magnetic layer. R AP. WL. SL.

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Presentation Transcript
stt ram generator

STT-RAM Generator

- Anurag Nigam

motivation
Challenges in SRAM

High Leakage

Solution

Non-volatile memory

Leakage current

Motivation
stt ram bit cell overview

Hard Ferro magnetic layer

BL

Oxide layer

MTJ

RP

Free Ferro magnetic layer

RAP

WL

SL

STT-RAM bit cell overview

MTJ

  • 1 MTJ
  • 1 access transistor
bit cell design
Bit-cell Design
  • IMTJ = f (Vin, parameters)
  • Behavioral current source
  • Need to solve differential equation
  • How to solve differential equation ??
bit cell design1

componentName = isource

I = f(V)

Bit-cell design
  • Editing CDF parameter to create behavioral source
bit cell design2

WL

BL=0V

SL=1V

Switching

Write “1” Operation

Bit-cell design

Schematic

memory interface

STT-RAM Macro

Data In

Write Driver

R/W

Data In

CLK

WLen

R/W

Timing Block

Data Out

CLK

ADDR

Memory Array

R’/W

ADDR

CL

WLS

Sensing Block

SAen

Data Out

Memory Interface
write driver

TBUF

BL

TBUF

SL

Write Driver
  • Write “1”  BL =0 SL=1
  • Write “0”  BL=1 SL=0
r v characteristic of mtj

RAP

RP

R-V characteristic of MTJ
  • Two states (RAP and RP)
  • Resistance is a function of voltage
schematic automation
Schematic automation
  • Leaf-cell schematic creation
    • Bitcells – Manual (using current/voltage sources)
    • Decoders – Skill
    • Sense amp. Timing block, Write driver – Manual
  • Memory array creation
    • 1Kb array - Skill
schematic automation1
Schematic automation
  • Decoder

procedure(Create7to128DecoderSchematic(libname,cellname))

  • Write Driver

procedure(CreateWriteDrSchematic(libname,cellname,C))

  • Memory Array

procedure(CreateSTTRAMSchematic(libname,cellname,R,C))

1kb stt ram array

128 x 8 array

Write Driver

Timing block

Sense amplifier

1Kb STT-RAM array
read and write operation

Read “1”

Write “0”

Read ”0”

Write “1”

clk

Out<0>

Data<0>

Read and Write operation
deliverables
Deliverables
  • STT-RAM bit-cell SPICE model
  • Skill script to generate complete functional STT-RAM
  • Class-specific work
    • Importing bit-cell model in ADE
    • Skill script development
ad