CS4101 嵌入式系統概論 Interrupt

1 / 38

# CS4101 - PowerPoint PPT Presentation

CS4101 嵌入式系統概論 Interrupt. 金仲達教授 國立清華大學資訊工程學系. 11/22/2010. (Slides from An Embedded Software Primer , David E. Simon, Addison Wesley). Outline. Interrupt basics Interrupt in 8051 Shared data problem in interrupt. Recall Your Earlier Mission. An intrusion detection system. Spotlight.

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.

## PowerPoint Slideshow about 'CS4101 ' - mike_john

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

### CS4101 嵌入式系統概論Interrupt

11/22/2010

(Slides fromAn Embedded Software Primer, David E. Simon, Addison Wesley)

Outline

Interrupt basics

Interrupt in 8051

Shared data problem in interrupt

An intrusion detection system

Spotlight

Camera

Motiondetector

Controller

The motion detectors will track the intruder and direct the spotlight and camera to follow the intruder

System Design

USB

CPU

Serial

Memory

Serial

PCM7230

What software is needed on PCM7230to read PIR’s through 8051?

Now, Focus on 8051+PIR
• Need to know:
• Which PIR is triggered
• Time sequence of their triggering
How Did 8051 Know PIR Triggered?

This is called ...?

void main (void) {

...

P3_6 = 1; //set PIR port input

P3_7 = 1; //set switch port input

...

while (1) { /* Loop forever */

while (P3_6 == 0 && P3_7 == 1 && ...) ...; // loop

if (P3_7 == 0) { ... }// switch is active low

else if (P3_6 == 1 ) { ... } // PIR is active high

else if ...

}

Analogy: Checking for Boiling Soup

This is called polling and it wastes your time!

Open the covers one by one and round-robin

If the soup in a pot boils, then handle that pot

(http://icons.mysitemyway.com)

How to Avoid Wasting Your Time?

Interrupt

• Do other things and come back later
• How do you know time is up and you should come back?

 need a clock and notification

• How do you know how long you can be away?

 you can try not to go away for too long

 you can guess (e.g., based on past experiences)

 you can ask the pots to notify you

How Interrupt Works for You?

You are free to do any other things

When the soup in a pot boils, the pot will notify you by giving you a signal and interrupting whatever you are doing

You remember where you are interrupted

You return and check to see which pot sent you the interrupt and what services it requests

You follow the instructions as requested to do the service

You return to the interrupted work after you are done with the requested services

Interrupt Basics

Interrupts are triggered when certain events occur in the hardware

Usually done by sending a signal to one of the processor’s IRQ (interrupt request) pins

Interrupt Service Routine

An interrupt signal stops the processor at the next instruction and the processor saves the address of the next instruction on the stack and jumps to the interrupt service routine (ISR) or interrupt handler

ISR is basically a subroutine to perform certain operations to handle the interrupt with a RETURN instruction at the end

It is a good practice to save register state and reset the interrupt in ISRs

ISRs are similar to a CALL except that the call to the ISR is automatically made

Interrupt Service Routine

The following shows an example of an ISR

...

MOVE R1, R7

MUL R1, 5 PUSH R1

DIV R1, 2 ...

JCOND ZERO, END ;ISR code comes here

SUBTRACT R1, R3 ...

... POP R2

... POP R1

END: MOVE R7, R1 RETURN

... ...

Saving and Restoring the Context

The task code has no idea of the changes taking place in registers like R1 or R2 in the ISR

If R1 is modified by the ISR, we might get an incorrect final result.

Due to limited number of registers, the ISRs and task codes usually have to work with same registers.

To solve this problem it is common practice to save the register contents onto the stack (saving the context) and restoring them at the end of the ISR (restoring the context).

Disabling Interrupts

Programs may disable interrupts

In most cases the program can select which interrupts to disable during critical operations and which to keep enabled by writing corresponding values into a special register.

Nonmaskable interrupts cannot be disabled and are used to indicate power failures or serious event.

Certain processors assign priorities to interrupts, allowing programs to specify a threshold priority so that only interrupts having higher priorities than the threshold are enabled and the ones below it are disabled.

Some Common Questions
• How does processor know where to find ISR?
• ISR is at a fixed location, e.g., in 8051, the first interrupt pin always causes 8051 to jump to 0x0003
• A table in memory contains addresses of ISR these addresses are called interrupt vector the table is called interrupt vector table
• How does processor know where interrupt vector table is?
• At a fixed location, e.g., 0x00000 for Intel 80186
• Devices provide the interrupt vectors
• Programs may set the location of the table
• ...
Some Common Questions
• Can a processor be interrupted in the middle of an instruction?
• Usually not
• Exceptions: critical hardware failure, long-running instructions (e.g. moving data in memory)
• If two interrupts occur at the same time, which ISR does the process do first?
• Prioritize the interrupt signals
• Can an interrupt signal interrupt another ISR?
• Interrupt nesting usually allowed according to priority
• Some processor may require re-enabling by your ISR
Some Common Questions
• What happens when an interrupt is signaled while the interrupt is disabled?
• Processors usually remember the interrupt signals and jump to the ISR when the interrupt is enabled
• What happens when we forget to re-enable disabled interrupts?
• What happens if we disable a disabled interrupt?
• Are interrupts enabled or disabled when the processor first starts up?
Outline

Interrupt basics

Interrupt in 8051

Shared data problem in interrupt

Interrupts in 8051

Original 8051 has 6 sources of interrupts

Reset

Timer 0 overflow

Timer 1 overflow

External Interrupt 0

External Interrupt 1

Serial Port events

P1

P0

RESET

P3

P2

Interrupt Vectors

Each interrupt has a specific place in program memory where execution of interrupt service routine begins

Note: only 8 memory locations between vectors

Writing the ISR

Example: ISR for Timer0 interrupt

ORG 0000H ;reset

LJMP MAIN

ORG 000BH ;Timer0 entry point

T0ISR: . ;Timer0 ISR begins

.

MAIN: . ;main program

.

.

END

When an Interrupt Occurs

Following actions are taken by 8051:

The current Program Counter is saved on the stack, low-byte first.

Interrupts of the same and lower priority are blocked.

In the case of Timer and External interrupts, the corresponding interrupt flag is cleared.

Program execution transfers to the corresponding interrupt handler vector address.

The Interrupt Handler Routine executes.

When an Interrupt Ends

An interrupt ends when the ISR executes the RETI (Return from Interrupt) instruction.

The following actions are taken by 8051:

Two bytes are popped off the stack into the Program Counter to restore normal program execution.

Interrupt status is restored to its pre-interrupt status

Interrupt Enable (IE) Register

EA ---- ET2 ES ET1 EX1 ET0 EX0

• All interrupt are disabled after reset
• Must be enabled by software for 8051 to respond to
• Done by the 8-bit Interrupt Enable Register (IE)
• EA: Global enable/disable
• ES: Serial interface
• ET1: Timer 1
• EX1: External interrupt 1
• ET0: Timer 0
• EX0: External interrupt 0 (0=Disabled, 1=Enabled)
Enabling and Disabling an Interrupt

SETB IE.7

SETB IE.1

SETB IE.3

SETB IE.0

SETB IE.2SETB IE.4

• By bit operation:

SETB EA ;Enable All

SETB ET0 ;Enable Timer0 ovrf

SETB ET1 ;Enable Timer1 ovrf

SETB EX0 ;Enable INT0

SETB EX1 ;Enable INT1

SETB ES ;Enable Serial port

• By Mov instruction:

MOV IE, #10010110B

Example

A 10khz square wave with 50% duty cycle

ORG 0 ;Reset entry point

LJMP MAIN ;Jump above interrupt

ORG 000BH ;Timer 0 interrupt vector

T0ISR:CPL P1.0 ;Toggle port bit

RETI ;Return from ISR to Main prog

ORG 0030H ;Main Program entry point

MAIN: MOV TMOD,#02H ;Timer 0, mode 2

MOV TH0,#-50 ;50 us delay

SETB TR0 ;Start timer

MOV IE,#82H ;Enable timer 0 interrupt

SJMP \$ ;Do nothing just wait

END

Interrupt Priorities

What if two interrupt sources interrupt at the same time?

The interrupt with the highest PRIORITY gets serviced first.

All interrupts have a power on default order.

External interrupt 0 (INT0)

Timer interrupt0 (TF0)

External interrupt 1 (INT1)

Timer interrupt1 (TF1)

Serial communication (RI+TI)

Priority can be set to “high” or “low” by IP reg.

IP: Interrupt Priority Register

PS : Serial interface

PT1: Timer 1

PX1: External interrupt 1

PT0: Timer 0

PX0: External interrupt 0

0 = Low priority

1 = High priority

----- ----- PT2 PS PT1 PX1 PT0 PX0

Interrupt Priorities

A low-priority interrupt can be interrupted by high-priority interrupt, but not by another low-priority one

A high-priority interrupt can’t be interrupted by any other interrupt source

If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced, so within each priority lever there is a second priority structure

Outline

Interrupt basics

Interrupt in 8051

Shared data problem in interrupt

The Shared-Data Problem

In many cases the ISRs need to communicate with the task codes through shared variables.

Example:

Task code monitors 2temperatures and alarm if they differ

An ISR reads temperatures from hardware

The Shared-Data Problem

Now, consider the assembly code:

When temperatures are 70 degrees and an interrupt occurs between the two MOVES

The temperatures now become 75 degrees

On returning from ISR, iTemp[1] will be assigned 75 and an alarm will be set off even though the temperatures were the same

The Shared-Data Problem

Problem is due to shared array iTemperatures.

These bugs are very difficult to find as they occur only when the interrupt occurs in between the first 2 MOVE instructions, other than which code works perfectly.

Solving Shared-Data Problem

Disable interrupts during instructions that use the shared variable and re-enabling them later

while (TRUE)

{

disable(); // Disable interrupts

iTemp0 = iTemperatures[0];

iTemp1 = iTemperatures[1];

enable(); // Re-enable interrupts

...

}

Solving Shared-Data Problem

“Atomic” and “Critical Section”

A part of a program that be interrupted

Example:

An ISR that updates iHours, iMinutes and iSeconds every second through a hardware timer interrupt:

long iSecondsSinceMidnight (void) {

long lReturnVal;

disable();

lReturnVal =

(((iHours*60)+iMinutes)*60)+iSeconds; enable();

return (lReturnVal);

}

Interrupt Latency

Interrupt latency is the amount of time taken to respond to an interrupt. It depends on:

Longest period during which the interrupt is disabled

Time to execute ISRs of higher priority interrupts

Time for processor to stop current execution, do the necessary ‘bookkeeping’ and start executing the ISR

Time taken for the ISR to save context and start executing instructions that count as a ‘response’

Make ISRs short

Factors 4 and 2 are controlled by writing efficient code that are not too long.

Factor 3 depends on HW, not under software control