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C hapter 4 Henry Hexmoor-- SIUC

Rudimentary Logic functions: Value fixing Transferring Inverting. C hapter 4 Henry Hexmoor-- SIUC. Functions and Functional Blocks. The functions considered are those found to be very useful in design

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C hapter 4 Henry Hexmoor-- SIUC

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  1. Rudimentary Logic functions: • Value fixing • Transferring • Inverting Chapter 4Henry Hexmoor-- SIUC Henry Hexmoor

  2. Functions and Functional Blocks • The functions considered are those found to be very useful in design • Corresponding to each of the functions is a combinational circuit implementation called a functional block. • In the past, many functional blocks were implemented as SSI, MSI, and LSI circuits. • Today, they are often simply parts within a VLSI circuits. Henry Hexmoor

  3. Rudimentary Logic Functions • Functions of a single variable X • Can be used on theinputs to functionalblocks to implementother than the block’sintended function Value fixing transfer V or V inverting CC DD 1 F = 1 F = 1 X F = X (c) 0 F = 0 F = 0 X F = X (a) (b) (d) Henry Hexmoor

  4. A A Multiple-bit Rudimentary Functions • Multi-bit Examples: • A wide line is used to representa bus which is a vector signal • In (b) of the example, F = (F3, F2, F1, F0) is a bus. • The bus can be split into individual bits as shown in (b) • Sets of bits can be split from the bus as shown in (c)for bits 2 and 1 of F. • The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F. • See Example 4-1 F 3 2 3 1 2:1 F(2:1) 2 F 1 4 4 2 F F 0 0 F 1 1 0 (c) A A F 0 3 (a) (b) 3,1:0 F(3), F(1:0) 4 F (d) Henry Hexmoor

  5. Enabling Function • Enabling permits an input signal to pass through to an output • Disabling blocks an input signal from passing through to an output, replacing it with a fixed value • See Example 4-2 Automobile… Henry Hexmoor

  6. Decoding4-3 • Decoding - the conversion of an n-bit input code to an m-bit output code withn £ m £ 2n such that each valid code word produces a unique output code • Circuits that perform decoding are called decoders • Here, functional blocks for decoding are • called n-to-m line decoders, where m£ 2n, and • generate 2n (or fewer) minterms for the n input variables Henry Hexmoor

  7. n inputs n to 2n decoder 2n outputs : : Binary n-to-2n Decoders • A binary decoder has n inputs and 2n outputs. • Only the output corresponding to the input value is equal to 1. Henry Hexmoor

  8. Decoder Examples A D D 0 1 • 1-to-2-Line Decoder D = A 0 0 1 0 1 0 1 D = A A 1 (a) (b) Henry Hexmoor

  9. Note that the 2-4-line made up of 2 1-to-2- line decoders and 4 AND gates. Decoder Examples A 0 A A D D D D 1 0 0 1 2 3 A 1 0 0 1 0 0 0 D = A A 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 D = A A 1 1 0 0 0 1 1 1 0 (a) D = A A 2 1 0 D = A A 3 1 0 (b) Henry Hexmoor

  10. Decoder Expansion - Example • 3-to-8-line decoder • Number of output ANDs = 8 • Number of inputs to decoders driving output ANDs = 3 • Closest possible split to equal • 2-to-4-line decoder • 1-to-2-line decoder • 2-to-4-line decoder • Number of output ANDs = 4 • Number of inputs to decoders driving output ANDs = 2 • Closest possible split to equal • Two 1-to-2-line decoder Henry Hexmoor

  11. Decoder Expansion – 3-to-8 line Example • Result Henry Hexmoor

  12. n-to-m line: An n bit binary code is converted to a unique m bit binary pattern • See Figure 4-6 for 1-to-2 line decoder • Let k = n. • If k is even, divide k by 2 to obtain k/2. Use 2k AND gates driven by two decoders of output size 2k/2. • If k is odd, obtain (k+1)/2 and (k-1)/2, Use 2K AND gates driven by a decoder of output size 2(k-1)/2. • For each decoder resulting from step 2, repeat step 2 with k equal to the values obtained in step 2 until K = 1. For k = 1, use a 1-to-2 decoder. CS 315:Decoding4-3 OR Gate A Henry Hexmoor

  13. Decoder Expansion • General procedure given in book for any decoder with n inputs and 2n outputs. • This procedure builds a decoder backward from the outputs. • The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1. • These decoders are then designed using the same procedure until 1-to-2-line decoders are reached. • The procedure can be modified to apply to decoders with the number of outputs ≠ 2n Henry Hexmoor

  14. /Bl D C B A a b c d e f g 0 x x x x 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 -- don’t care inputs -- Decoder Example: Seven-Segment Decoders • A seven segment decoder has 4-bit BCD input and the seven segment display code as its output: • In minimizing the circuits for the segment outputs all non-decimal input combinations (1010, 1011, 1100,1101, 1110, 1111) are taken as don’t-cares Henry Hexmoor

  15. Decoder Expansion - Example • 7-to-128-line decoder • Number of output ANDs = 128 • Number of inputs to decoders driving output ANDs = 7 • Closest possible split to equal • 4-to-16-line decoder • 3-to-8-line decoder • 4-to-16-line decoder • Number of output ANDs = 16 • Number of inputs to decoders driving output ANDs = 2 • Closest possible split to equal • 2 2-to-4-line decoders • Complete using known 3-8 and 2-to-4 line decoders Henry Hexmoor

  16. Decoder with Enable • In general, attach m-enabling circuits to the outputs • See truth table below for function • Note use of X’s to denote both 0 and 1 • Combination containing two X’s represent four binary combinations • Alternatively, can be viewed as distributing value of signal EN to 1 of 4 outputs • In this case, called ademultiplexer Henry Hexmoor

  17. Encoding4-4 • Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n£ m£ 2n such that each valid code word produces a unique output code • Circuits that perform encoding are called encoders • An encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values • Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corres-ponding to the position in which the 1 appears. Henry Hexmoor

  18. Encoder n > m Y0 Y1 … Y n-1 I0 I1 I2 … I2n-1 Encoder n outputs 2n inputs 0th bit OR0 I1,I3, I5, I7 Y0 = 0001 + 0011 + 0101 + 0111 I2, I3, I6, I7 OR1 y1 y2 OR2 I4, I5, I6, I7 2n – n encoder requires “n 2n-1 input” OR gates Bit j of input code is connected to OR gate j if bit j in the input is 1. Encoders are useful when the occurrence of one of several disjoint events needs to be represented by an integer identifying the event. E.g., wind direction encoder Henry Hexmoor

  19. Encoder Example 1 Henry Hexmoor

  20. Encoder Example 2 • A decimal-to-BCD encoder • Inputs: 10 bits corresponding to decimal digits 0 through 9, (D0, …, D9) • Outputs: 4 bits with BCD codes • Function: If input bit Di is a 1, then the output (A3, A2, A1, A0) is the BCD code for i, • The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly. Henry Hexmoor

  21. Encoder Example (continued) • Input Diis a term in equation Aj if bit Aj is 1 in the binary value for i. • Equations: A3 = D8 (1000) + D9 (1001) A2 = D4 (0100)+ D5 (0101) + D6 (0110)+ D7 (0111) A1 = D2 (0010)+ D3 (0011) + D6 (0110) + D7 (0111) A0 = D1 (0001)+ D3 (0011)+ D5 (0101) + D7 (0111) + D9 (1001) • F1 = D6 + D7 can be extracted from A2 and A1. Henry Hexmoor

  22. Priority Encoder • If more than one input value is 1, then the encoder just designed does not work. • One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder. • Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position. • Priority encoders are useful when inputs have a predefined priority, e.g., interrupt requests from peripheral devices Henry Hexmoor

  23. A1 = D3’D2 + D3 A0 = D3’D2’D1 + D3 V = D0 + D1+ D2+ D3 Priority Encoder Example • Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to most significant 1 present - Code outputs A2, A1, A0 and V where V indicates at least one 1 present. • Xs in input part of table represent 0 or 1; thus table entries correspond to product terms instead of minterms. The column on the left shows that all 32 minterms are present in the product terms in the table Henry Hexmoor

  24. Selecting4-5 • Selecting of data or information is a critical function in digital systems and computers • Circuits that perform selecting have: • A set of information inputs from which the selection is made • A single output • A set of control lines for making the selection • Logic circuits that perform selecting are called multiplexers • Selecting can also be done by three-state logic or transmission gates Henry Hexmoor

  25. Multiplexers • A multiplexer selects information from an input line and directs the information to an output line • A typical multiplexer has n control inputs (Sn - 1, … S0) called selection inputs, 2n information inputs (I2n- 1, … I0), and one output Y • A multiplexer can be designed to have m information inputs with m < 2n as well as n selection inputs Henry Hexmoor

  26. Selecting4-5 Multiplexers, data selectors 2n input lines + n selection inputs See 2-to-1-line multiplexer in Figure 4-13 Two input lines and one select line S Y = S’I0 + S I1 OR Gate A Henry Hexmoor

  27. 2-to-1-Line Multiplexer • The single selection variable S has two values: • S = 0 selects input I0 • S = 1 selects input I1 • The equation: Y = S’I0 + SI1 • The circuit: Henry Hexmoor

  28. 2-to-1-Line Multiplexer (continued) • Note the regions of the multiplexer circuit shown: • 1-to-2-line Decoder • 2 Enabling circuits • 2-input OR gate • To obtain a basis for multiplexer expansion, we combine the Enabling circuits and OR gate into a 2 ´ 2 AND-OR circuit: • 1-to-2-line decoder • 2 ´ 2 AND-OR • In general, for an 2n-to-1-line multiplexer: • n-to-2n-line decoder • 2n´ 2 AND-OR Henry Hexmoor

  29. Decoder S 1 4 2 AND-OR S 0 Decoder Decoder S S 1 1 S S I 0 0 0 Y Y I 1 Y I 2 I 3 Example: 4-to-1-line Multiplexer: n = 2 selection bits • 2-to-22-line decoder • 22´ 2 AND-OR Henry Hexmoor

  30. Multiplexer Width Expansion • Select “vectors of bits” instead of “bits” • Use multiple copies of 2n ´ 2 AND-OR in parallel • Example:4-to-1-linequad multi-plexer • Figure 4-16 Henry Hexmoor

  31. Using Multiplexers • Any Boolean function can be implemented by setting the inputs corresponding to the function as inputs and the selectors as the variables. Henry Hexmoor

  32. Shifters Henry Hexmoor

  33. Rotator Henry Hexmoor

  34. Parity for six bit messages Even Parity Generator Circuit B 0 B 1 B 2 B 3 B 4 B even B 5 B 6 Even Parity Checker Circuit B 0 B 1 B 2 B 3 B 4 B 5 ERROR B 6 B even Henry Hexmoor

  35. Gray Binary A B C x y z 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 1 Example: Gray to Binary Code • Design a circuit to convert a 3-bit Gray code to a binary code • The formulation givesthe truth table on theright • It is obvious from thistable that X = C and theY and Z are more complex Henry Hexmoor

  36. F = C F = C F = C F = C F = C F = C F = C F = C Gray to Binary (continued) • Rearrange the table so that the input combinations are in counting order, pair rows, and find rudimentary functions Henry Hexmoor

  37. C C D10 D00 D11 C C C C C D01 C D12 Y Out Z D02 Out C C D13 D03 8-to-1 8-to-1 A A S1 S1 MUX MUX S0 S0 B B Gray to Binary (continued) • Assign the variables and functions to the multiplexer inputs: Henry Hexmoor

  38. Combinational Function Implementation4-6 • Alternative implementation techniques: • Decoders and OR gates • Multiplexers (and inverter) • ROMs • PLAs • PALs • Lookup Tables • Can be referred to as structured implementation methods since a specific underlying structure is assumed in each case Henry Hexmoor

  39. Read Only Memory • Functions are implemented by storing the truth table • Other representations such as equations more convenient • Generation of programming information from equations usually done by software • Text Example 4-10 Issue • Two outputs are generated outside of the ROM • In the implementation of the system, these two functions are “hardwired” and even if the ROM is reprogrammable or removable, cannot be corrected or updated Henry Hexmoor

  40. A B C X X X 1 X 2 X X X X X Fuse intact Fuse blown 1 X X X 3 X X 4 X X X 0 X C C B B A A 1 X F 1 F 2 Programmable Logic Array Example Henry Hexmoor

  41. Lookup Tables • Lookup tables are used for implementing logic in Field-Programmable Gate Arrays (FPGAs) and Complex Logic Devices (CPLDs) • Lookup tables are typically small, often with four inputs, one output, and 16 entries • Since lookup tables store truth tables, it is possible to implement any 4-input function • Thus, the design problem is how to optimally decompose a set of given functions into a set of 4-input two- level functions. Henry Hexmoor

  42. HW 4 • Draw the detailed logic diagram of a 3-to-8-line decoder using only NOR and NOT gates. Include an enable input. Q4-9 • Implement a binary full adder with a dual 4-to-1-line multiplexer and a single inverter. Q4-23 Henry Hexmoor

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