Spezielle anwendungen des vlsi entwurfs applied vlsi design
Download
1 / 8

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design - PowerPoint PPT Presentation


  • 97 Views
  • Uploaded on

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design. Course and contest Results of Phase 4 Nam Pham Van. Design comparison. P ~ A Power: P = ( P dyn * P leak ) Area: A  Reduction of the area  lower the power consumption. Design & architecture.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design' - michiko-hanabishi


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Spezielle anwendungen des vlsi entwurfs applied vlsi design

Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design

Course and contest

Results of Phase 4

Nam Pham Van


Design comparison
Design comparison

P ~ A Power: P = (Pdyn * Pleak)

Area: A

 Reduction of the area  lower the power consumption


Design architecture
Design & architecture

  • RCA  small area  low power consumption

  • Improve speed with Carry Skip architecture


Design architecture optimization
Design & architecture optimization

  • Adder Reduction:

  • 10 bit  8 bit

  • 11 bit  10 bit

  • 16 bit  13 bit

  • Influences:

  • Minimized switch activity

  • Reduced area & power consumption


Cadence configuration
Cadenceconfiguration

Setting Effect

  • Netlist optimization

  • Design optimization

  • Higher frequency are possible

  • Power consumption raised immense

  • Antenna fixing

  • Eco route

  • Wire optimization

  • No impact

  • Other gate libraries

  • Higher frequency are possible

  • Extreme high leakage power consumption


Cadence configuration1
Cadenceconfiguration

  • Best settings:

  • Core Ratio H/W: 1

  • Core Utilization: 90

  • IO Boundary: 15

  • Power Ring:

    • Width: 2

    • Spacing: 0.5

    • Offset: 2

  • COREHVTtyp10V




ad