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Phase Detector Circuits

Phase Detector Circuits. Presented by: Ricky Lau. Outline. Why this topic? Common Phase Detectors (PD) in industry Novel Phase Detector design Future design challenges of Phase Detectors. Why this topic?.

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Phase Detector Circuits

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  1. Phase Detector Circuits Presented by: Ricky Lau

  2. Outline • Why this topic? • Common Phase Detectors (PD) in industry • Novel Phase Detector design • Future design challenges of Phase Detectors

  3. Why this topic? • Clock and Data Recovery Systems (CDR) are extensively used in telecommunication and digital systems • Phase Detector is critical to the performance of a CDR system

  4. Linear vs Bang-Bang PD

  5. Hogge Phase Detector • Static phase error due to CK->Q delay of FF • Low output jitter and retimes data

  6. Alexander Phase Detector • High output jitter • Maintain VCO frequency even when no data transition • Retimes Data

  7. Improved Bang-Bang PD • Large freq steps enhance pull-in range • Small freq steps reduce output jitter • Half-Rate Architecture

  8. Future Challenges • Jitter performance • Pull-in range • Sensitivity to input data patterns • Reliability • Analog vs Digital PD

  9. Questions?

  10. References • M. Ramezani, C.A.T. Salama, "An Improved Bang-Bang Phase Detector for Clock and Data Recovery Applications“, ISCAS, Vol.1, pp.715-718, 2001. • B. Razavi, “Challenges in the design high-speed clock and data recovery circuits”, IEEE communications Magazine, Vol.40, Issue 8, pp. 94-101, Aug. 2002. • S. Soliman, F. Yuan, K. Raahemifar, “An overview of design techniques for CMOS phase detectors”, ISCAS, Vol.5, pp.26-29, May 2002. • M. Rau, T. Oberst, R. Lares, A. Rothermel, R. Schweer, N. Menoux, “Clock/Data Recovery PLL Using Half-Frequency Clock”, IEEE Journal of Solid-State Circuits, pp.1156-1160, 1997. • J. Savoj, B. Razavi, “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half Rate Linear Phase Detector,” IEEE Journal of Solid-State Circuits, Vol.36, pp.761-768, May 2001

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