SYSTEM HARDENING – UPSET RECOVERY MACRO CELL LIBRARY

1. SYSTEM HARDENING – UPSET RECOVERY MACRO CELL LIBRARY Marion Rose – Peter Coakley – Dennis Breuner Jaycor, Inc. 3394 Carmel Mountain Road San Diego, CA 92121 Sponsor: DTRA – Maj. Chris McCormack Contract: DSWA01-99-C-0180

2. AFRL BOEING (ANAHEIM) BOEING (HUNTSVILLE) HUGHES LOCKHEED MARTIN MISSILES & SPACE LOCKHEED MARTIN SANDERS RAYTHEON SPECTRUM ASTRO TELEDYNE BROWN ENGINEERING TRW SHUR Participants PROGRAM MANAGEMENT JAYCOR TECHNICAL ADVISORS RECOVERY TIMELINE REDUCTION Lead - JAYCOR Deputy - SAIC DEMONSTRATION ASIC Lead - JAYCOR Fab - Honeywell, SSEC SYSTEM REQUIREMENTS Lead - JAYCOR Deputy - SAIC

3. Program Objective Develop and Demonstrate a Library of Macro Cells to Implement System Hardening – Upset Recovery (SHUR) in Application Specific Integrated Circuits (ASICs) and Programmable Logic Devices (PLDs)

4. Applications for SHUR Functions You should consider SHUR if: • Your system relies on critical data to complete its mission • Your system needs to detect and recover from electronic upsets • Your system must recover rapidly from upset • Your system relies on HW/SW to control upset recovery • Your system uses COTS in a nuclear environment Offers Recovery Insurance

5. Critical Data Protected With SHUR • SHUR functions are memory mapped • Address and data protected via gate keeper • Access time penalty near 30 ns Ensures Integrity of Critical Data

6. Command and Control FunctionsPassed Through SHUR • When upset is detected: • Prevents critical data corruption • Prevents execution of erroneous commands • Monitors interruption time • Initiates rapid data/system recovery As a “Gate Keeper” SHUR Preserves Signal Integrity

7. SHUR Develops and DemonstratesUpset Recovery Technologies SHUR Demonstrates Upset and Recovery Applications

8. SHUR Technology Products • SHUR provides system designers • Library of upset and recovery building blocks (macro cells) • Performance specifications for library cells • Application guidelines for using library cells • ASIC demonstrating SHUR building block performance • POD’s for contractor evaluation • Software recommendations for rapid recovery SHUR Provides the Building Blocks -- You Provide the Creative Engineering

9. SHUR Performance Goals • Transient upset level > 1E11 rad(Si)/s • Dose rate survive level > 1E12 rad(Si)/s • Latchup None • Ionizing dose threshold > 1E6 rad(Si) • Neutron fluence > 1E14 n/cm2 • SEE > 1E-10 errors/bit/day • Operating frequency > 100 MHz • Temperature –55oC to +125oC

10. HX2000r Gate Array Family Specifications • Operates over full –55oC to +125oC temperature • No latchup • SEU up to 1E-10 error/bit/day (Adams 10% worst case environment) • Total dose hardness to 1E6 rad(Si) • Prompt dose upset level depends on package and fixturing • Can have full in-system power down capability • Compatible with both 3.3V and 5V logic levels • Family of gate arrays:

11. Preliminary VHDL Design Testbench and Simulation SHUR Function Design Definition HX2000r Synthesis Preliminary VHDL Design Testbench and Simulation SHUR Function Design Definition Parallel I/O Parallel interface False write protection Last address retention Read-write decoder Internal register file SRAM interface Fault processing Fault mask Restart control Warm-start flag Event counter Startup timer Off-line timer Time-of-day clock Yes Yes Yes Yes Yes Yes Yes In process Yes Yes Yes Yes TBD Yes Yes Yes Yes Yes In process Yes TBD TBD TBD In process Yes TBD Yes Yes Yes Yes Yes TBD Yes TBD TBD TBD TBD Yes TBD Yes Yes Yes TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD System clock generation Crystal oscillator Phase-locked loop Clock generation Clock frequency select Divide by 2 Divide by 3 Divide by 5 Divide by 10 Divide by 22 Clock distribution General Purpose I/O Discrete Inputs Discrete Outputs Strobe generator Comd./control interfaces Yes In process Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes TBD Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes TBD Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Yes Yes TBD TBD SHUR Macro Cell Library Status HX2000r Synthesis

12. Port Description Name Type Function CLK I System clock NSM_SEL I Selects SHUR function (low) NRESET I Resets logic during power-up (low) INHIBIT I Halts generation of NHWR (low) NHWR O Delayed write pulse ( ) NLATCH O Latches data into SHUR register (low) DMACK O Memory acknowledge False-Write Macro Features • Latches address and data into internal SHUR registers • Delays write pulse to non-upsettable memory to ensure data integrity (30 ns minimum) • Generates memory acknowledge signal for processors using automatic wait-state allocation Timing

13. High Dose Rate Glitchless Clock 50 MHz 3rd Overtone Pierce Oscillator SHUR Approach for Clock Generation • Demonstrated in Harris TS0S-4 ASIC technology • L1 and C2 critical for crystal mode selection and IEMP mitigation • Robust designs >50 MHz problematic • PLL generates integer multiples of reference clock frequency • Facilitates use of more robust fundamental gate oscillator

14. SHUR Functions: Protecting Data and Commands SHUR Functions Accessed Like Memory

15. Example of Components in DSP System

16. Example of SHUR Components in DSP System

17. SHUR Functional Implementationin a Multiple Processor Subsystem

18. SHUR Integration Into System Design SHUR Functions Provide Flexible Upset Recovery Solutions

19. SHUR Program Schedule

20. Summary • Ensures command & control signal integrity • Protects critical data • Enables rapid recovery from upset, minimizing potential outage • Gives flexibility to design and battle space trades • Is a COTS enabler Offers Upset Recovery Assurance