1 / 21

Basics of Multi-rule Systems Arvind Computer Science & Artificial Intelligence Lab.

Basics of Multi-rule Systems Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology September 17, 2009. x. inQ. sReg1. sReg2. outQ. f1. f2. f3. Synchronous Pipeline. Red and Green tokens must move even if there is nothing in the inQ!.

mervin
Download Presentation

Basics of Multi-rule Systems Arvind Computer Science & Artificial Intelligence Lab.

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Basics of Multi-rule Systems Arvind Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology September 17, 2009 http://csg.csail.mit.edu/korea

  2. x inQ sReg1 sReg2 outQ f1 f2 f3 Synchronous Pipeline Red and Green tokens must move even if there is nothing in the inQ! rule sync-pipeline (True); inQ.deq(); sReg1 <= f1(inQ.first()); sReg2 <= f2(sReg1); outQ.enq(f3(sReg2)); endrule Also if there is no token in sReg2 then nothing should be enqueued in the outQ Valid bits or the Maybe type Modify the rule to deal with these conditions http://csg.csail.mit.edu/korea

  3. x inQ sReg1 sReg2 outQ f1 f2 f3 Synchronous Pipeline using the Maybe type data rule sync-pipeline (True); if (inQ.notEmpty()) begin sReg1 <= Valid f1(inQ.first()); inQ.deq(); end elsesReg1 <= Invalid; case (sReg1) matches tagged Valid .sx1: sReg2 <= Valid f2(sx1); tagged Invalid: sReg2 <= Invalid; case (sReg2) matches tagged Valid .sx2: outQ.enq(f3(sx2)); endrule http://csg.csail.mit.edu/korea

  4. f1 f2 f3 Asynchronous pipelineUse FIFOs instead of pipeline registers x inQ fifo1 fifo2 outQ rule stage1 (True); fifo1.enq(f1(inQ.first()); inQ.deq(); endrule rule stage2 (True); fifo2.enq(f2(fifo1.first()); fifo1.deq(); endrule rule stage3 (True); outQ.enq(f3(fifo2.first()); fifo2.deq(); endrule Firing conditions? Can tokens be left inside the pipeline? No Maybe types? Easier to write? http://csg.csail.mit.edu/korea

  5. Asynchronous pipeline: Some Issues • Easier to write but will not behave like a pipeline unless all rules can execute simultaneously • It must be possible to enqueue and dequeue in a FIFO simultaneously http://csg.csail.mit.edu/korea

  6. Rule scheduling and the synthesis of a scheduler http://csg.csail.mit.edu/korea

  7. Highly non-deterministic Guarded Atomic Actions (GAA):Execution model Repeatedly: • Select a rule to execute • Compute the state updates • Make the state updates User annotations can help in rule selection Implementation concern: Schedule multiple rules concurrently without violating one-rule-at-a-time semantics http://csg.csail.mit.edu/korea

  8. Rule: As a State Transformer A rule may be decomposed into two parts p(s) and d(s) such that snext = if p(s) then d(s) elses p(s)is the condition (predicate) of the rule, a.k.a. the “CAN_FIRE” signal of the rule. p is a conjunction of explicit and implicit conditions d(s) is the “state transformation” function, i.e., computes the next-state values from the current state values http://csg.csail.mit.edu/korea

  9. Compiling a Rule rule r (f.first() > 0) ; x <= x + 1 ; f.deq (); endrule enable p f f x x d current state next state values rdy signals read methods enable signals action parameters p = enabling condition d = action signals & values http://csg.csail.mit.edu/korea

  10. R d1,R dn,R Combining State Updates: strawman p1 p’s from the rules that update R OR pn latch enable OR d’s from the rules that update R next state value What if more than one rule is enabled? http://csg.csail.mit.edu/korea

  11. R d1,R dn,R Combining State Updates f1 one-rule-at-a-time scheduler is conservative Scheduler: Priority Encoder p1 OR p’s from all the rules pn fn latch enable OR d’s from the rules that update R next state value Scheduler ensures that at most one fi is true http://csg.csail.mit.edu/korea

  12. One-rule-at-a-time Scheduler p1 Scheduler: Priority Encoder f1 p2 f2 pn fn 1. fi  pi 2. p1  p2  ....  pn  f1  f2  ....  fn 3. One rewrite at a time i.e. at most one fi is true Very conservative way of guaranteeing correctness http://csg.csail.mit.edu/korea

  13. A compiler can determine if two rules can be executed in parallel without violating the one-rule-at-a-time semantics James Hoe, Ph.D., 2000 http://csg.csail.mit.edu/korea

  14. Executing Multiple Rules Per Cycle:Conflict-free rules rule ra (z > 10); x <= x + 1; endrule rule rb (z > 20); y <= y + 2; endrule Parallel execution behaves like ra < rb or equivalently rb < ra Rulea and Ruleb are conflict-free if s . pa(s)  pb(s)  1. pa(db(s)) pb(da(s)) 2. da(db(s)) ==db(da(s)) Parallel Execution can also be understood in terms of a composite rule rule ra_rb; if (z>10) then x <= x+1; if (z>20) then y <= y+2; endrule http://csg.csail.mit.edu/korea

  15. Mutually Exclusive Rules • Rulea and Ruleb are mutually exclusive if they can never be enabled simultaneously s . pa(s)  ~ pb(s) Mutually-exclusive rules are Conflict-free by definition http://csg.csail.mit.edu/korea

  16. - R(rb) is the range of rule rb - Prjst is the projection selecting st from the total state Executing Multiple Rules Per Cycle:Sequentially Composable rules rule ra (z > 10); x <= y + 1; endrule rule rb (z > 20); y <= y + 2; endrule Rulea and Ruleb are sequentially composable if s . pa(s)  pb(s)  1. pb(da(s)) 2. PrjR(rb)(db(s)) == PrjR(rb)(db(da(s))) Parallel execution behaves like ra < rb Parallel Execution can also be understood in terms of a composite rule rule ra_rb; if (z>10) then x <= x+1; if (z>20) then y <= y+2; endrule http://csg.csail.mit.edu/korea

  17. p1 f1 Scheduler p2 f2 Scheduler Scheduler pn fn Multiple-Rules-per-Cycle Scheduler Divide the rules into smallest conflicting groups; provide a scheduler for each group 1. fi  pi 2. p1  p2  ....  pn  f1  f2  ....  fn 3.Multiple operations such that fi  fj  Ri and Rj are conflict-free or sequentially composable http://csg.csail.mit.edu/korea

  18. Compiler determines if two rules can be executed in parallel Rulea and Ruleb are conflict-free if s . pa(s)  pb(s)  1. pa(db(s)) pb(da(s)) 2. da(db(s)) ==db(da(s)) D(Ra)  R(Rb) =  D(Rb)  R(Ra) =  R(Ra)  R(Rb) =  Rulea and Ruleb are sequentially composable if s . pa(s)  pb(s)  1. pb(da(s)) 2. PrjR(Rb)(db(s)) == PrjR(Rb)(db(da(s))) D(Rb)  R(Ra) =  These conditions are sufficient but not necessary These properties can be determined by examining the domains and ranges of the rules in a pairwise manner. Parallel execution of CF and SC rules does not increase the critical path delay http://csg.csail.mit.edu/korea

  19. Conflict Free/Mutually Exclusive) d1 p1 d2 d2 p2 p2 Sequentially Composable d1 p1 and ~p2 and and or or and and Muxing structure • Muxing logic requires determining for each register (action method) the rules that update it and under what conditions If two CF rules update the same element then they must be mutually exclusive (p1 ~p2) http://csg.csail.mit.edu/korea

  20. p1 pn d1 dn Scheduling and control logic Modules (Current state) Modules (Next state) “CAN_FIRE” “WILL_FIRE” Rules p1 f1 Scheduler fn pn d1 Muxing cond action dn Compiler synthesizes a scheduler such that at any given time f’s for only non-conflicting rules are true http://csg.csail.mit.edu/korea

  21. f1 f2 f3 Does our pipeline behave properly? x inQ fifo1 fifo2 outQ rule stage1 (True); fifo1.enq(f1(inQ.first()); inQ.deq(); endrule rule stage2 (True); fifo2.enq(f2(fifo1.first()); fifo1.deq(); endrule rule stage3 (True); outQ.enq(f3(fifo2.first()); fifo2.deq(); endrule Can all three rules fire concurrently? next time http://csg.csail.mit.edu/korea

More Related