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Performance-Impact Limited Area Fill Synthesis

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Supported by Cadence Design Systems, Inc. and MARCO/DARPA GSRC

Performance-Impact Limited Area Fill Synthesis

Yu Chen

UbiTech, Inc.

Puneet Gupta, Andrew B. Kahng

Univ. of California, San Diego

http://vlsicad.ucsd.edu

- Chemical Mechanical Planarizationand Area Fill
- Performance-Impact Limited (PIL) Fill Problem
- Capacitance and Delay Models
- Approaches for PIL-Fill Problems
- Computational Experiences
- Conclusion and Future Works

- Chemical-Mechanical Planarization (CMP)
- Polishing pad wear, slurry composition, pad elasticity make this a very difficult process step

silicon wafer

slurry feeder

wafer carrier

polishing pad

slurry

polishing table

- Area fill feature insertion
- Decreases local density variation
- Decreases the ILD thickness variation after CMP

Post-CMP ILD thickness

Features

Area fill

features

w

w/r

tile

Overlapping windows

n

- To make filling more tractable, monitor only fixed set of w w windows
- offset = w/r (example shown: w = 4, r = 4)

- Partition n x n layout intonr/w nr/wfixed dissections
- Each w w window is partitioned into r2 tiles

- Objective for Manufacture = Min-Var
minimize window density variation

subject to upper bound on window density

- Objective for Design= Min-Fill
minimize total amount of added fill features

subject to upper bound on window density variation

- Kahng et al.
- First LP-based approach for Min-Var objective
- Monte-Carlo/greedy method
- Iterated Monte-Carlo/greedy method
- Monte-Carlo methods for hierarchical fill problem and multiple-layer fill problem

- Wong et al.
- LP-based approaches for Min-Fill objective
- LP-based approaches for multiple-layer fill problem and dual-material fill problem

- Chemical Mechanical Planarization and Area Fill
- Performance-Impact Limited (PIL) Fill Problem
- Capacitance and Delay Models
- Approaches for PIL-Fill Problems
- Computational Experiences
- Conclusion and Future Works

- Why?
- Fill features insertion to reduce layout density variation
change coupling capacitance

change interconnect signal delay and crosstalk

- Current methods: no consideration of performance impact during fill synthesis

- Fill features insertion to reduce layout density variation

Timing Closure Error ?

Filled layout

- General guidelines:
- Minimize total number of fill features
- Minimize fill feature size
- Maximize space between fill features
- Maximize buffer distance between original and fill features

- Sample observations in literature
- Motorola [Grobman et al., 2001]
key parameters are fill feature size and buffer distance

- Samsung [Lee et al., 2003]
floating fills must be included in chip-level RC extraction and timing analysis to avoid timing errors

- MIT MTL [Stine et al., 1998]
proposed a rule-based area fill methodology to minimize added interconnect coupling capacitance

- Motorola [Grobman et al., 2001]

- Problem Formulation
- Two objectives:
- minimize layout density variation due to CMP
- minimize fill features' impact on circuit performance

- In general, cannot minimize two objectives simultaneously
- minimize one objective while keeping the other as constraints

- Two objectives:

- Two formulations for PIL Fill problem
- Min-Delay-Fill-Constrained (MDFC) objective
- Max-MinSlack-Fill-Constrained (MSFC) objective

- Given
- A fixed-dissection routed layout
- Design rule for floating square fill features
- Prescribed amount of fills in each tile
- Direction of current flow in each tile
- Per-unit length resistance for interconnect segment in each tile

- Fill layout such that
- Performance impact (i.e., total increase in wire segment delay) is minimized

- Insert fill features into each tile such that
- Total impact on delay is minimized

- Weakness of MDFC objective
- can not directly consider the impact due to fill features on the signal delay of complete timing paths

- Given
- A fixed-dissection routed layout
- Design rule for floating square fill features
- Prescribed amount of fills in each tile

- Fill layout such that
- minimum slack over all nets in the layout is maximized

- Chemical Mechanical Planarization and Area Fill
- Performance-Impact Limited (PIL) Fill Problem
- Capacitance and Delay Models
- Approaches for PIL-Fill Problems
- Computational Experiences
- Conclusion and Future Works

- Interconnect capacitance consists of
- Overlap Cap. : surface overlap of two conductors
- Coupling Cap. : two parallel conductors on the same plane
- Fringe Cap. : two conductors on different planes

- Mainly consider fill impact on coupling capacitance

- Elmore Delay Model
- First moment of impulse response for a distributed RC interconnect
- Enjoys additivityproperty with respect to capacitance along any source-sink path

- Elmore Delay of RC Tree

slack site

column

- Grid layout with fill feature size into sites
- Slack Site Column: column of available sites for fill features between active lines

top view

Active

lines

w

fill grid

pitch

buffer distance

- Per-unit capacitance between two active lines separated by distance d, with m fill features in one column:

- Slack site columns in fixed-dissection regime
- Between active line and tile boundary
- Between active lines in adjacent tiles

- Advantage
- Possible impact of fill feature at any position can be considered

1

2

Tile

A

B

C

Active

lines

3

7 slack blocks

D

E

4

5

F

G

6

- Find out slack columns (within each tile) between pairs of active lines in adjacent tiles
- Scan whole layout from bottom (left) boundary for horizontal (vertical) routing direction

1

2

Tile

A

B

C

Active

lines

3

7 slack blocks

D

E

4

5

F

G

6

- Chemical Mechanical Planarization and Area Fill
- Performance-Impact Limited (PIL) Fill Problem
- Capacitance and Delay Models
- Approaches for PIL-Fill Problems
- Computational Experiences
- Conclusion and Future Works

- #RequiredFills obtained from normal fill synthesis
- Objective:
minimize weighted incremental delay due to fill features

Minimize:

: num of downstream sinks of segment

- Based on pre-built lookup table for coupling capacitance calculation
- Fill features have the same shape
- Potential num of fill features in each column is limited
- Other parameters are constant for the whole layout

- Constraints:
Binary:

1. for each column

2. for all overlapping columns

# used slack sites = # fill features

3.for each column

incremental cap. due to features in each column

4.for each segment

total Elmore delay increment

5.# used slack sites column size

- Run standard fill synthesis to get #RequiredFills for each tile
- For each net Do
- Find intersection with each tile
- Calculate entry resistances of net in its intersecting tiles

- Get slack site columns by scan-line algorithm
- For each tile Do
- For each slack column Do
- calculate induced coupling capacitance of slack column

- Sort all slack columns according to its corresponding delay
- While #RequiredFills > 0 Do
- select slack column with minimum corresponding delay
- insert features into the slack column

- For each slack column Do

Partition the given layout into tiles and sites

Run normal area fill synthesis:

required fills (RFij) for each tile,

total number of requires fills (RF)

Scan whole layout to get all slack site columns

Iterated Approaches for MSFC PIL-Fill

- Pre-Steps:

- Reduced Standard Parasitic Format (RSPF) file
- Interface between Static Timing Analysis and fill synthesis

- Iteration variables
- LBslack: lower bound on slack value of slack site columns
- UBdelay: upper bound on total added delay during one iteration

Choose slack site column k with

maximum slack value Smax

Run STA tool with RSPF file to get slacks for all input pins

Yes

Smax< LBslack

Dadd > UBdelay

Calculate slack for

each active line

Run STA

max number of feasible

fills for column k

Calculate slack value for

each slack site column

min

overlapping size of

column k in tile

Get #fills to be inserted for each

tile intersecting with column k

number of required

fills for tile

Calculate added delay Dadd

Calculate max number of feasible fills for slack site column k

Yes

Update RSPF file

with capacitance increase

Decrease LBslack

Yes

No

DF > 0

End

Iterated Approaches for MSFC PIL-Fill

- Chemical Mechanical Planarization and Area Fill
- Performance-Impact Limited (PIL) Fill Problem
- Capacitance and Delay Models
- Approaches for PIL-Fill Problems
- Computational Experiences
- Conclusion and Future Works

- Testbed
- C++ under Solaris
- CPLEX 7.0 as linear programming solver
- 300 MHz Sun Ultra-10 with 1GB RAM

- Test cases
- In LEF/DEF format
- Signal delay calculation based on RSPF file
- Use previous LP/Monte-Carlo methods as normal fill synthesis (Chen et al. TCAD02)

- PIL-Fill methods are better than normal fill method

- LUT based ILP has better performance but longer runtime

- Iterated greedy method for MSFC PIL-Fill only decrease minimum slack of all nets by 7% (min), 20% (average), 37% (max)
significant improvement

- Chemical Mechanical Planarization and Area Fill
- Performance-Impact Limited (PIL) Fill Problem
- Capacitance and Delay Models
- Approaches for PIL-Fill Problems
- Computational Experiences
- Conclusion and Future Works

Contributions:

Approximation for performance impact due to area fill insertion

First formulations for Performance-Impact Limited Fill problem

ILP-based and greedy-based methods for MDFC PIL-Fill problem

Iterated greedy-based method for MSFC PIL-Fill problem

- Future Works
- Budget slacks along segments avoid iteration with STA
- Consider impact due to fill on overlap and fringe capacitance
- Other PIL-Fill formulations
- Min density variation while obeying upper bound on timing impact

Thank You!