Coping with interconnect
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COPING WITH INTERCONNECT PowerPoint PPT Presentation


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COPING WITH INTERCONNECT. Impact of Interconnect Parasitics. Nature of Interconnect. INTERCONNECT. Capacitance: The Parallel Plate Model. Typical Wiring Capacitance Values. Fringing Capacitance. Fringing Capacitance: Values. How to counter Clock Skew?. Interwire Capacitance.

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COPING WITH INTERCONNECT

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COPING WITH INTERCONNECT


Impact of Interconnect Parasitics


Nature of Interconnect


INTERCONNECT


Capacitance: The Parallel Plate Model


Typical Wiring Capacitance Values


Fringing Capacitance


Fringing Capacitance: Values


How to counter Clock Skew?


Interwire Capacitance


Interwire Capacitance


Impact of Interwire Capacitance


Capacitance Crosstalk


How to Battle Capacitive Crosstalk


Driving Large Capacitances


Using Cascaded Buffers


tp in function of u and x


Impact of Cascading Buffers


Output Driver Design


How to Design Large Transistors


Bonding Pad Design

Bonding Pad

GND

100 mm

Out

VDD

Out

In

GND


Reducing the swing

  • Reducing the swing potentially yields linear reduction in delay

  • Also results in reduction in power dissipation

  • Requires use of “sense amplifier” to restore signal level


Charge Redistribution Amplifier


Precharged Bus


Tristate Buffers


Using Bipolar Versus MOS

But: Bipolar does not scale well with voltage!


Bipolar Versus MOS (cont.)


INTERCONNECT


Wire Resistance


Interconnect Resistance


Dealing with Resistance


Polycide Gate Mosfet


Modern Interconnect


RI Introduced Noise


Power and Ground Distribution


Electromigration (1)


Electromigration (2)


RC-Delay


RC-Models


Reducing RC-delay

Repeater


The Ellmore Delay


Penfield-Rubinstein-Horowitz


INTERCONNECT


Inductive Effects in Integrated Circuits


L di/dt


L di/dt: Simulation


Choosing the Right Pin


Decoupling Capacitors


The Transmission Line


Lossless Transmission Line - Parameters


Wave Propagation Speed


Wave Reflection for Different Terminations


Transmission Line Response (RL=)


Lattice Diagram


ECL Gate Line Response


Output Buffer Model


Output Buffer - Response


When to Consider Transmission Line Effects?


Packaging


Bonding Techniques


Tape-Automated Bonding (TAB)


Flip-Chip Bonding


Package-to-Board Interconnect


Package Types


Package Parameters


Multi-Chip Modules


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