Coping with interconnect
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COPING WITH INTERCONNECT. Impact of Interconnect Parasitics. Nature of Interconnect. INTERCONNECT. Capacitance: The Parallel Plate Model. Typical Wiring Capacitance Values. Fringing Capacitance. Fringing Capacitance: Values. How to counter Clock Skew?. Interwire Capacitance.

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COPING WITH INTERCONNECT

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Coping with interconnect

COPING WITH INTERCONNECT


Impact of interconnect parasitics

Impact of Interconnect Parasitics


Nature of interconnect

Nature of Interconnect


Interconnect

INTERCONNECT


Capacitance the parallel plate model

Capacitance: The Parallel Plate Model


Typical wiring capacitance values

Typical Wiring Capacitance Values


Fringing capacitance

Fringing Capacitance


Fringing capacitance values

Fringing Capacitance: Values


How to counter clock skew

How to counter Clock Skew?


Interwire capacitance

Interwire Capacitance


Interwire capacitance1

Interwire Capacitance


Impact of interwire capacitance

Impact of Interwire Capacitance


Capacitance crosstalk

Capacitance Crosstalk


How to battle capacitive crosstalk

How to Battle Capacitive Crosstalk


Driving large capacitances

Driving Large Capacitances


Using cascaded buffers

Using Cascaded Buffers


T p in function of u and x

tp in function of u and x


Impact of cascading buffers

Impact of Cascading Buffers


Output driver design

Output Driver Design


How to design large transistors

How to Design Large Transistors


Bonding pad design

Bonding Pad Design

Bonding Pad

GND

100 mm

Out

VDD

Out

In

GND


Reducing the swing

Reducing the swing

  • Reducing the swing potentially yields linear reduction in delay

  • Also results in reduction in power dissipation

  • Requires use of “sense amplifier” to restore signal level


Charge redistribution amplifier

Charge Redistribution Amplifier


Precharged bus

Precharged Bus


Tristate buffers

Tristate Buffers


Using bipolar versus mos

Using Bipolar Versus MOS

But: Bipolar does not scale well with voltage!


Bipolar versus mos cont

Bipolar Versus MOS (cont.)


Interconnect1

INTERCONNECT


Wire resistance

Wire Resistance


Interconnect resistance

Interconnect Resistance


Dealing with resistance

Dealing with Resistance


Polycide gate mosfet

Polycide Gate Mosfet


Modern interconnect

Modern Interconnect


Ri introduced noise

RI Introduced Noise


Power and ground distribution

Power and Ground Distribution


Electromigration 1

Electromigration (1)


Electromigration 2

Electromigration (2)


Rc delay

RC-Delay


Rc models

RC-Models


Reducing rc delay

Reducing RC-delay

Repeater


The ellmore delay

The Ellmore Delay


Penfield rubinstein horowitz

Penfield-Rubinstein-Horowitz


Interconnect2

INTERCONNECT


Inductive effects in integrated circuits

Inductive Effects in Integrated Circuits


L di dt

L di/dt


L di dt simulation

L di/dt: Simulation


Choosing the right pin

Choosing the Right Pin


Decoupling capacitors

Decoupling Capacitors


The transmission line

The Transmission Line


Lossless transmission line parameters

Lossless Transmission Line - Parameters


Wave propagation speed

Wave Propagation Speed


Wave reflection for different terminations

Wave Reflection for Different Terminations


Transmission line response r l

Transmission Line Response (RL=)


Lattice diagram

Lattice Diagram


Ecl gate line response

ECL Gate Line Response


Output buffer model

Output Buffer Model


Output buffer response

Output Buffer - Response


When to consider transmission line effects

When to Consider Transmission Line Effects?


Packaging

Packaging


Bonding techniques

Bonding Techniques


Tape automated bonding tab

Tape-Automated Bonding (TAB)


Flip chip bonding

Flip-Chip Bonding


Package to board interconnect

Package-to-Board Interconnect


Package types

Package Types


Package parameters

Package Parameters


Multi chip modules

Multi-Chip Modules


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