Built in adaptive test and calibration of dac
Download
1 / 22

Built-in Adaptive Test and Calibration of DAC - PowerPoint PPT Presentation


  • 93 Views
  • Uploaded on

Built-in Adaptive Test and Calibration of DAC. Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University, Auburn, AL 36849 18 th IEEE North Atlantic Test Workshop 2009. Outline. Overview Previous Work Proposed BIST Scheme Adaptive Self-Calibration of DAC

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Built-in Adaptive Test and Calibration of DAC' - meg


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Built in adaptive test and calibration of dac

Built-in Adaptive Test and Calibration of DAC

Wei Jiang and Vishwani D. Agrawal

Electrical and Computer Engineering

Auburn University, Auburn, AL 36849

18th IEEE North Atlantic Test Workshop 2009


Outline
Outline

  • Overview

  • Previous Work

  • Proposed BIST Scheme

  • Adaptive Self-Calibration of DAC

  • Simulation Results

  • Conclusion


Overview
Overview

  • Proposed design-for-testability (DFT) architecture for a mixed-signal SoC

    • Accuracy

    • Performance

    • Cost

  • Test of on-chip DAC and ADC

    • Linearity (DNL/INL)

    • Resolution and speed

    • Signal-to-noise ratio (SNR)


A typical mixed signal bist for soc
A Typical Mixed-Signal BIST for SoC*

* F. F. Dai and C. E. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter 15, p. 722 in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann, 2008.


Previous work
Previous Work

W. Jiang and V.D. Agrawal, Built-In Test and Calibration of DAC/ADC Using A Low-Resolution Dithering DAC, NATW’08


Non linearity errors
Non-linearity Errors

Non-linearity

error

Non-linearity

error



Proposed bist scheme cont
Proposed BIST Scheme (Cont.)

  • DSP for BIST control

  • Components

    • 1-bit first-order sigma-delta modulator

    • Low-pass filter (integrator or comb filter)

    • Adaptive polynomial evaluation/fix circuit

    • Low-resolution dithering DAC

    • Loop-back circuitry connecting internal DAC and ADC



Testing of dac cont
Testing of DAC (Cont.)

  • Response and ramp input compared for INL error

  • INL error analyzed by adaptive polynomial fitting algorithm

  • Best matching polynomials selected for various and DAC profiles

  • Test results indicated by calculated characteristics (offset, gain and harmonic distortion, etc)

  • Polynomial coefficients calculated for dithering DAC to improve INL


Polynomial fitting
Polynomial Fitting

  • Introduced by Sunter et al. in ITC’97 and A. Roy et al. in ITC’02

  • Summary:

    • Divide DAC transfer function into four sections

    • Combine function outputs of each section (S0, S1, S2, S3)

    • Calculate four coefficients (b0, b1, b2, b3) by easily-generated equations



First and second order polynomial
First- and second-order Polynomial

First-order polynomial

Second-order polynomial


Adaptive polynomial fitting
Adaptive Polynomial Fitting

  • Fitting INL error from lower order polynomial to higher order

  • Calculate RMS error of each polynomial

  • Select the polynomial with least RMS error (when RMS error rising with higher order polynomial)


Sigma delta modulator
Sigma-Delta Modulator

1-bit first-order sigma-delta modulator

Transfer function in z-domain


Sigma delta modulator cont
Sigma-Delta Modulator (Cont.)

SNR (dB)

Third-order

Second-order

17-bit ENOB104.1dB

First-order

Oversampling ratio (OSR)


Dithering dac
Dithering DAC

Estimated DAC resolution (bits)

Oversampling ratio (OSR)

α=1

2

3

17bits

Resolution of dithering-DAC (bits)


Simulation of dac test
Simulation of DAC Test

  • 14-bit DAC

  • 16K ramp codes

  • INL error up to ±1.5dB

INL of 14-bit DAC (LSB)

Indices of 14-bit DAC-under-test


Simulation cont
Simulation (Cont.)

INL of 14-bit DAC (LSB)

  • Fitting results by different order polynomial

Indices of 14-bit DAC-under-test



Conclusion
Conclusion

  • A built-in self-test and self-calibration solution for mixed-signal SoC is proposed

  • A polynomial fitting algorithm is employed for INL error correction

  • Fault-tolerance levels can be chosen for various applications

  • Simulation results show significant improvement in linearity after calibration


Q&A

Thank you!


ad